HYS6472V4200GU Datasheet, PDF (14/15 Pages) Siemens Semiconductor Group – 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module

SPD cont’d:
Byte#
Description
29 Minimum RAS to CAS delay tRCD
30 Minimum RAS pulse width tRAS
31 Module Bank Density (per bank)
32 SDRAM input setup time
33 SDRAM input hold time
34 SDRAM data input setup time
35 SDRAM data input hold time
32-61 Superset information
(may be used in future)
62 SPD Revision
63 Checksum for bytes 0 - 62
64- Manufacturers information (optional)
125 (FFh if not used)
126 Max. Frequency Specification
127 Support details
128+ Unused storage locations
HYS64(72)V4200/8220GU
SDRAM-Modules
SPD Entry
Value
24 ns
60 ns
32 MByte
2.5 ns
1 ns
2.5 ns
1 ns
Hex
4Mx64
-8
18
3C
08
25
10
25
10
FF
4Mx72
-8
18
3C
08
25
10
25
10
FF
8Mx72
-8
18
3C
08
25
10
25
10
FF
8Mx72
-8
18
3C
08
25
10
25
10
FF
Revision 1.2
12
12
12
12
7C
8E
7D
8F
XX
XX
XX
XX
66 MHz
66
66
66
66
AF
AF
FF
FF
FF
FF
FF
FF
Semiconductor Group
14