HYS6472V16200GU Datasheet, PDF (8/17 Pages) Siemens Semiconductor Group – 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules

HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Operating Currents
T_A = 0 to 70 °C, V_CC = 3.3 V ± 0.3 V ¹
Recommended Operating Conditions unless otherwise noted
Parameter & Test Condition
Symb.
Operating current
t_RC ≥ t_RC(MIN.), t_CK ≥ t_CK(MIN.)
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner to maximize
gapless data access
Precharged Standby Current in
Power Down Mode
CS = V_IH(MIN.), CKE ≤ V_IL(MAX.)
Precharged Standby Current in Non-
power Down Mode
CS = V_IH(MIN.), CKE ≥ V_IH(MIN.)
No operating current
t_CK = min., CS = V_IH(MIN.),
active state (max. 4 banks)
t_CK = min.
t_CK = min.
CKE ≥ V_IH(MIN.)
CKE ≤ V_IL(MAX.)
I_CC1
×4
×8
× 16
I_CC2P
I_CC2N
I_CC3N
I_CC3P
-8/-8B -10
max.
210 165
210 165
210 165
2
2
19
16
45
40
10
10
Unit Note
mA ²
mA
mA
mA ²
mA ²
mA ²
mA ²
Burst operating current
t_CK = min.,
Read command cycling
Auto refresh current
t_CK = min.,
Auto Refresh command cycling
Self refresh current
Self Refresh Mode, CKE = 0.2 V
–
I_CC4
×4
210
165
mA ^{2, 3}
×8
210 165 mA
× 16
210 165 mA
–
I_CC5
240 195 mA ²
standard version I_CC6
2.5
2.5
mA ²
Notes
1. All values are shown per one SDRAM component.
2. These parameters depend on the cycle rate. These values are measured at 100 MHz for -8
and at 66 MHz for -10 parts. Input signals are changed once during t_CK, excepts for I_CC6 and for
standby currents when t_CK = infinity.
3. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 is assumed and the V_DDQ current is excluded.
Semiconductor Group
8
1998-08-01