HYS6472V16200GU Datasheet, PDF (11/17 Pages) Siemens Semiconductor Group – 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules

HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Notes
1. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command
must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set
Operation can begin.
2. AC timing tests have V_IL = 0.4 V and V_IH = 2.4 V with the timing referenced to the 1.4 V
crossover point. The transition time is measured between V_IH and V_IL. All AC measurements
assume t_T = 1 ns with the AC output load circuit show. Specified t_AC and t_OH parameters are
measured with a 50 pF only, without any resisitve termination and with a input signal of 1 V/ns
edge rate between 0.8 V and 2.0 V.
CLOCK
t _CH
2.4 V
0.4 V
t _CL
t_T
t _SETUP
t _HOLD
INPUT
1.4 V
OUTPUT
t_AC
t _LZ
t_AC
t _OH
1.4 V
t _HZ
SPT03404
I/O
50 pF
Measurement conditions for
t_AC and t_OH
3. If clock rising time is longer than 1 ns, a time (t_T/2 – 0.5) ns has to be added to this parameter.
4. Rated at 1.5 V
5. If t_T is longer than 1 ns, a time (t_T – 1) ns has to be added to this parameter.
6. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up” the device.
7. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to t_RC is satisfied
once the Self Refresh Exit command is registered.
8. Referenced to the time which the output achieves the open circuit condition, not to output
voltage levels.
Semiconductor Group
11
1998-08-01