HYS6472V16200GU Datasheet, PDF (13/17 Pages) Siemens Semiconductor Group – 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules

HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
SPD-Table for 256MBit SDRAM based PC100 Modules (cont’d)
Byte# Description
SPD Entry
Value
Hex
32M×64 32M×64 32M×72 32M×72
one bank one bank one bank one bank
-8
-8B
-8
-8B
18
Supported CAS
Latencies
CAS latency = 2 06
06
06
06
&3
19
CS Latencies
CS latency = 0 01
01
01
01
20
WE Latencies
Write latency = 0 01
01
01
01
21
SDRAM DIMM module non buffered/ 00
00
00
00
attributes
non re.
22
SDRAM Device
V_CC tol ± 10% 06
06
06
06
Attributes: General
23
Min. Clock Cycle Time at 10.0 / 12.0 ns A0
C0
A0
C0
CAS Latency = 2
24
Max. data access time 6.0 / 7.0 ns
60
70
60
70
from Clock for CL = 2
25
Minimum Clock Cycle not supported FF
FF
FF
FF
Time at CL = 1
26
Maximum Data Access not supported FF
FF
FF
FF
Time from Clock at
CL = 1
27
Minimum Row Precharge 20 / 30 ns
14
1E
14
1E
Time
28
Minimum Row Active to 16 / 20 ns
10
14
10
14
Row Active delay t_RRD
29
Minimum RAS to CAS 20 ns
delay t_RCD
14
14
14
14
30
Minimum RAS pulse
50 / 60 ns
32
3C
32
3C
width t_RAS
31
Module Bank Density
256 MByte
40
40
40
40
(per bank)
32
SDRAM input setup time 2 ns
20
20
20
20
33
SDRAM input hold time 1 ns
10
10
10
10
34
SDRAM data input hold 2 ns
time
20
20
20
20
35
SDRAM data input setup 1 ns
time
10
10
10
10
Semiconductor Group
13
1998-08-01