HYS6472V16200GU Datasheet, PDF (15/17 Pages) Siemens Semiconductor Group – 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules

HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
SPD-Table for 256MBit SDRAM based PC100 Modules (cont’d)
Byte# Description
SPD Entry
Value
Hex
64M×64 64M×64 64M×72 64M×72
two bank two bank two bank two bank
-8
-8B
-8
-8B
10
SDRAM Access time
6.0 ns
from Clock at CL = 3
60
60
60
60
11
Dimm Configuration
none/ECC
00
00
02
02
12
Refresh Rate/Type
Self Refresh, 82
82
82
82
7.8 µs
13
SDRAMwidth,Primary × 8
08
08
08
08
14
Error Checking SDRAM n/a/× 8
data width
00
00
08
08
15
Minimum clock delay for t_CCD = 1 CLK
01
01
01
01
back-to-back random
column address
16
Burst Length supported 1, 2, 4, 8 & full 8F
8F
8F
8F
page
17
Number of SDRAM
4
banks
04
04
04
04
18
Supported CAS
Latencies
CAS latency = 2 06
06
06
06
&3
19
CS Latencies
CS latency = 0 01
01
01
01
20
WE Latencies
Write latency = 0 01
01
01
01
21
SDRAM DIMM module non buffered/ 00
00
00
00
attributes
non re.
22
SDRAM Device
V_CC tol ± 10% 06
06
06
06
Attributes: General
23
Min. Clock Cycle Time at 10.0/12.0 ns
A0
C0
A0
C0
CAS Latency = 2
24
Max. data access time 6.0/7.0 ns
60
70
60
70
from Clock for CL = 2
25
Minimum Clock Cycle not supported FF
FF
FF
FF
Time at CL = 1
26
Maximum Data Access not supported FF
FF
FF
FF
Time from Clock at
CL = 1
27
Minimum Row Precharge 20/30 ns
Time
14
1E
14
1E
Semiconductor Group
15
1998-08-01