HYB314100BJBJL-50- Datasheet, PDF (7/23 Pages) Siemens Semiconductor Group – 4M x 1-Bit Dynamic RAM Low Power 4M x 1-Bit Dynamic RAM

HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
AC Characteristics ⁵⁾⁶⁾
T_A = 0 to 70 ˚C, V_CC = 3.3 V ± 0.3 V, t_T = 5 ns
Parameter
Symbol
Limit Values
Unit Note
-50
-60
-70
min. max. min. max. min. max.
Common Parameters
Random read or write cycle time t_RC
95 –
110 –
130 –
ns
RAS precharge time
t_RP
35 –
40 –
50 –
ns
RAS pulse width
t_RAS 50 10k 60 10k 70 10k ns
CAS pulse width
t_CAS 13 10k 15 10k 20 10k ns
Row address setup time
t_ASR
0
–
0
–
0
–
ns
Row address hold time
t_RAH
8
–
10 –
10 –
ns
Column address setup time
t_ASC
0
–
0
–
0
–
ns
Column address hold time
t_CAH
10 –
15 –
15 –
ns
RAS to CAS delay time
t_RCD 18 37 20 45 20 50 ns
RAS to column address delay t_RAD 13 25 15 30 15 35 ns
time
RAS hold time
CAS hold time
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
Refresh period for L-version
t_RSH
13
15 –
20 –
ns
t_CSH
50
60 –
70 –
ns
t_CRP
5
–
5
–
5
–
ns
t_T
3
50 3
50 3
50 ns 7
t_REF
–
16 –
16 –
16 ms
t_REF
–
128 –
128 –
128 ms
Read Cycle
Access time from RAS
Access time from CAS
Access time from column
address
t_RAC
–
t_CAC
–
t_AA
–
50 –
13 –
25 –
60 –
15 –
30 –
70 ns 8, 9
20 ns 8, 9
35 ns 8,10
Column addr. to RAS lead time t_RAL 25 –
Read command setup time
t_RCS
0
–
Read command hold time
t_RCH
0
–
Read command hold time
referenced to RAS
t_RRH
0
–
30 –
0
–
0
–
0
–
35 –
0
–
0
–
0
–
ns
ns
ns 11
ns 11
CAS to output in low-Z
t_CLZ
0
–
0
–
0
–
ns 8
Semiconductor Group
7