HYB314100BJBJL-50- Datasheet, PDF (22/23 Pages) Siemens Semiconductor Group – 4M x 1-Bit Dynamic RAM Low Power 4M x 1-Bit Dynamic RAM

HYB 314100BJ/BJL-50/-60/-70
3.3V 4M x 1 DRAM
Test Mode Entry
Test Mode
The HYB314100BJ/BJL is organized 4 194 304 words by 1- bit but can internally be configured as
524 288 words by 8-bits. A WE, CAS-before-RAS cycle puts the device into Test Mode.
In Test Mode, data is written into 8 sectors in parallel and retrieved the same way. If, upon reading,
all bits are equal, the data output pin indicates a “1”. If any of the bits differ, the data output pin
indicates a “0”. In Test Mode the 4M DRAM can be tested as if it were a 512K DRAM. Test Mode
is exited by any refresh operation which is not a WE, CAS- before-RAS cycle. Addresses A10R,
A10C and A0C do not care during Test Mode.
Semiconductor Group
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