PEB22554 Datasheet, PDF (55/397 Pages) Siemens Semiconductor Group – ICs for Communications

PEB 22554
Functional Description E1
3.6 Transmit Path
Compared to the receive paths the inverse functions are performed for the transmit
direction.
The interface to the transmit system highway is realized by two data buses, one for the
data XDI and one for the signaling data XSIG. The time-slot assignment is equivalent to
the receive direction.
Latching of data is controlled by the System Clock (SCLKX) and the Synchronous Pulse
(SYPX / XMFS) in conjunction with the programmed offset values for the Transmit
Time-slot/Clock-slot Counters XC1/0. The frequency of the working clock of 2.048 /
4.096 / 8.192 / 16.384 MHz for the transmit system interface is programmable by
SIC1.SSC1/0. Refer also table 4.
The received bit stream on ports XDI and XSIG could be multiplexed internally on a
time-slot basis, if enabled by SIC3.TTRF = 1. The data received at port XSIG could be
sampled if the transmit signaling marker XSIGM is active high. Data at port XDI will be
sampled if XSIGM is low for the respective time-slot. Programming the XSIGM marker is
done with registers TTR1-4.
SYPX
125 µs
SCLKX
XDI
T
TS31
TS0
TS1
0123456701234567
XSIG
A B C D FAS / NFAS
ABCD
T = Time-Slot Offset (Register XC1/0)
FAS = Frame Alignment Signal
NFAS = TS0 not containing the FAS word
ABCD = Signaling Bits for Time-Slot 1-30 of CAS Multiframe
Figure 19
2.048 MHz Transmit Signaling Highway
Semiconductor Group
55
TS31
01234567
ABCD
ITT10518
09.98