PEB22554 Datasheet, PDF (204/397 Pages) Siemens Semiconductor Group – ICs for Communications

PEB 22554
7
Functional Description T1 / J1
7.1 Functional Block Diagram
Functional Description T1 / J1
RCLK(1-4)
FALC 4
FALC 3
FALC 2
FALC 1
Receive Jitter
Attenuator
SCLKR(1-4)
RL1/RDIP/
ROID(1-4)
RL2/RDIN/
RCLKI(1-4)
XL1/XDOP/
XOID(1-4)
XL2/XDON/
XFM(1-4)
Long+Short
Haul Line
Interface
Clock/Data
Recovery
Long + Short
Haul Transmit
Line Interface
Receive Framer
Alarm Detector
PRBS Monitor
Line Decoder
Perform. Monitor.
Receive Elastic
Buffer
or
Bypass
Signaling
Controller
CAS-CC
CAS-BR
Frame Gen.
Alarm Gen.
PRBS Generator
Line Coding
Transmit Elastic
Buffer
or
Bypass
Receive
Backplane
Interface
HDLC/BOM
Controller
Transmit
Backplane
Interface
Transmit Jitter
Attenuator
TCLK
RCLK
RDO(1-4)
RPA(1-4)
RPB(1-4)
RPC(1-4)
RPD(1-4)
XDI(1-4)
XPA(1-4)
XPB(1-4)
XPC(1-4)
XPD(1-4)
SCLKX(1-4)
RCLK
TCLK SCLKX
(1-4)
(1-4) (1-4)
Boundary Scan
JTAG 1149
Microprocessor Interface
Intel/Motorola
Clocking Unit
TDI TMS TCK TRS TDO D0...15 A0...9 WR/RW ALE IM DBW INT
CS RD/DS BHE/BLE RES
Figure 38 Functional Block Diagram PEB 22554
Semiconductor Group
204
MCLK SYNC SEC/FSC
ITS10300
09.98