PEB22554 Datasheet, PDF (378/397 Pages) Siemens Semiconductor Group – ICs for Communications

PEB 22554
9.4.7 System Interface
RCLK (output)
1
2
3
4
RFSP
data valid
1) active edge can be programmed to be positive or negative (only negative edge timing shown here)
valid only, if RCLK is derived from DPLL (not, if RCLK is jitter attenuated)
RFSP
Figure 85
RCLK, RFSP Output Timing
Table 38
RCLK, RFSP Timing Parameter Values
No. Parameter
1 RCLK period E1 (2.048 MHz)
RCLK period E1 (2.048 MHz x 4)
RCLK period T1 (1.544 MHz)
RCLK period T1 (1.544 MHz x 4)
2 RCLK pulse high
3 RCLK pulse low
4 RFSP delay
Limit Values
Unit
min. typ. max.
488
ns
122
ns
648
ns
162
ns
40
60 %
40
60 %
80 ns
Semiconductor Group
378
09.98