PEB22554 Datasheet, PDF (227/397 Pages) Siemens Semiconductor Group – ICs for Communications

PEB 22554
Functional Description T1 / J1
Table 18
System Clocking and Data Rates
System Data Rate Clock Rate
1.544 / 2.048
MHz
1.544/ 2.048 MBit/s x
3.088/ 4.096 MBit/s --
6.176/ 8.192 MBit/s --
12.352 /
--
16.384 MBit/s
Clock Rate
3.088 / 4.096
MHz
x
x
--
--
Clock Rate
6.176 / 8.192
MHz
x
x
x
--
Clock Rate
12.352 /
16.384 MHz
x
x
x
x
x = valid , -- = invalid
Generally the data or marker on the system interface are clocked off or latched on the
rising or falling edge (SIC3.RESR/X) of the SCLKR/X clock. Some clocking rates allow
transmitting of time-slots in different channel- phases. Each channel-phase which should
be active on ports RDO, XDI, RP(A-D) and XP(A-D) is programmable by bit
SIC2.SICS2-0, the remaining channel-phases are cleared or ignored.
The signals on pin SYPR in conjunction with the assigned timeslot offset in register RC0
and RC1 will define the beginning of a frame on the receive system highway.The signal
on pin SYPX in conjunction with the assigned timeslot offset in register XC0 and XC1 will
define the beginning of a frame on the transmit system highway.
Adjusting the frame begin (time-slot 0, bit 0) relative to SYPR/X is possible in the range
of 0 - 125 µsec. The minimum shift of varying the time-slot 0 begin could be programmed
between 1 bit and 1/8 bit depending of the system clocking and data rate. e.g. with a
clocking / data rate of 2.048 MHz shifting is done bitwise, while running the QuadFALC
with 16.384 MHz and 2.048 MBit/s data rate it is done by 1/8 bit.
A receive frame marker RFM could be activated during any bit position of the entire
frame. Programming is done with registers RC1/0. The pin function RFM is selected by
PC(1-4).RPC(2-0) = 001. The RFM selection disables the internal time-slot assigner, no
offset programming is performed. The receive frame marker is active high for one 1.544
/ 2.048 MHz cycle and is clocked off with the rising or falling edge of the clock which is
in/output on port SCLKR.
Semiconductor Group
227
09.98