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| PEB22554 Datasheet, PDF (287/397 Pages) Siemens Semiconductor Group – ICs for Communications | |||
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MDS2-0â¦
BRACâ¦
HRACâ¦
DIVâ¦
PEB 22554
Operational Description T1 / J1
Mode Select
The operating mode of the HDLC controller is selected.
000⦠Reserved
001⦠Reserved
010⦠1 byte address comparison mode (RAL1, 2)
011⦠2 byte address comparison mode (RAH1, 2 and RAL1, 2)
100⦠No address comparison
101⦠1 byte address comparison mode (RAH1, 2)
110⦠Reserved
111⦠No HDLC framing mode 1
BOM Receiver Active
Switches the BOM receiver to operational or inoperational state.
0⦠Receiver inactive
1⦠Receiver active
HDLC Receiver Active
Switches the HDLC receiver to operational or inoperational state.
0⦠Receiver inactive
1⦠Receiver active
Data Inversion
Setting this bit will invert the internal generated HDLC data stream.
0⦠normal operation, HDLC data stream not inverted
1⦠HDLC data stream inverted
Receive Address Byte High Register 1 (Read/Write)
Value after RESET: FDH
7
RAH1
10
0
(x04)
In operating modes that provide high byte address recognition, the high byte of the
received address is compared with the individually programmable values in RAH1 and
RAH2.
RAH1â¦
Value of the First Individual High Address Byte
Bit 1 (C/R-bit) is excluded from address comparison.
Semiconductor Group
287
09.98
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