C165_96 Datasheet, PDF (40/283 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

10Jul97@15:33^Th^{he Central Processing Unit (CPU) / C165/C163}
4 The Central Processing Unit (CPU)
Basic tasks of the CPU are to fetch and decode instructions, to supply operands for the arithmetic
and logic unit (ALU), to perform operations on these operands in the ALU, and to store the
previously calculated results. As the CPU is the main engine of the C165/C163 controller, it is also
affected by certain actions of the peripheral subsystem.
Since a four stage pipeline is implemented in the C165/C163, up to four instructions can be
processed in parallel. Most instructions of the C165/C163 are executed in one machine cycle (ie.
100 ns @ 20 MHz CPU clock) due to this parallelism. This chapter describes how the pipeline works
for sequential and branch instructions in general, and which hardware provisions have been made
to speed the execution of jump instructions in particular. The general instruction timing is described
including standard and exceptional timing.
While internal memory accesses are normally performed by the CPU itself, external peripheral or
memory accesses are performed by a particular on-chip External Bus Controller (EBC), which is
automatically invoked by the CPU whenever a code or data address refers to the external address
space. If possible, the CPU continues operating while an external memory access is in progress. If
external data are required but are not yet available, or if a new external memory access is requested
by the CPU, before a previous access has been completed, the CPU will be held by the EBC until
the request can be satisfied. The EBC is described in a dedicated chapter.
Figure 4-1
CPU Block Diagram
Semiconductor Group
4-1