C165_96 Datasheet, PDF (18/283 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

10Jul97@15:33h
Architectural Overview / C165/C163
Programmable Multiple Priority Interrupt System
The following enhancements have been included to allow processing of a large number of interrupt
sources:
1) Peripheral Event Controller (PEC): This processor is used to off-load many interrupt requests
from the CPU. It avoids the overhead of entering and exiting interrupt or trap routines by per-
forming single-cycle interrupt-driven byte or word data transfers between any two locations in
segment 0 with an optional increment of either the PEC source or the destination pointer.
Just one cycle is ’stolen’ from the current CPU activity to perform a PEC service.
2) Multiple Priority Interrupt Controller: This controller allows all interrupts to be placed at any
specified priority. Interrupts may also be grouped, which provides the user with the ability to
prevent similar priority tasks from interrupting each other. For each of the possible interrupt
sources there is a separate control register, which contains an interrupt request flag, an inter-
rupt enable flag and an interrupt priority bitfield. Once having been accepted by the CPU, an
interrupt service can only be interrupted by a higher prioritized service request. For standard
interrupt processing, each of the possible interrupt sources has a dedicated vector location.
3) Multiple Register Banks: This feature allows the user to specify up to sixteen general pur-
pose registers located anywhere in the internal RAM. A single one-machine-cycle instruction
allows to switch register banks from one task to another.
4) Interruptable Multiple Cycle Instructions: Reduced interrupt latency is provided by allowing
multiple-cycle instructions (multiply, divide) to be interruptable.
With an interrupt response time within a range from just 250 ns to 500 ns (in case of internal
program execution), the C165/C163 is capable of reacting very fast on non-deterministic events.
Its fast external interrupt inputs are sampled every 50 ns and allow to recognize even very short
external signals.
The C165/C163 also provides an excellent mechanism to identify and to process exceptions or
error conditions that arise during run-time, so called ’Hardware Traps’. Hardware traps cause an
immediate non-maskable system reaction which is similiar to a standard interrupt service
(branching to a dedicated vector table location). The occurrence of a hardware trap is additionally
signified by an individual bit in the trap flag register (TFR). Except for another higher prioritized trap
service being in progress, a hardware trap will interrupt any current program execution. In turn,
hardware trap services can normally not be interrupted by standard or PEC interrupts.
Software interrupts are supported by means of the ’TRAP’ instruction in combination with an
individual trap (interrupt) number.
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