C165_96 Datasheet, PDF (28/283 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

10Jul97@15:33h
Architectural Overview / C165/C163
General Purpose Timer (GPT) Unit
The GPT units represent a very flexible multifunctional timer/counter structure which may be used
for many different time related tasks such as event timing and counting, pulse width and duty cycle
measurements, pulse generation, or pulse multiplication.
The five 16-bit timers are organized in two separate modules, GPT1 and GPT2. Each timer in each
module may operate independently in a number of different modes, or may be concatenated with
another timer of the same module.
Each timer can be configured individually for one of three basic modes of operation, which are
Timer, Gated Timer, and Counter Mode. In Timer Mode the input clock for a timer is derived from
the internal CPU clock divided by a programmable prescaler, while Counter Mode allows a timer to
be clocked in reference to external events (via TxIN).
Pulse width or duty cycle measurement is supported in Gated Timer Mode where the operation of
a timer is controlled by the ‘gate’ level on its external input pin TxIN.
The count direction (up/down) for each timer is programmable by software or may additionally be
altered dynamically by an external signal (TxEUD) to facilitate eg. position tracking.
The core timers T3 and T6 have output toggle latches (TxOTL) which change their state on each
timer over-flow/underflow. The state of these latches may be output on port pins (TxOUT) or may be
used internally to concatenate the core timers with the respective auxiliary timers resulting in 32/33-
bit timers/counters for measuring long time periods with high resolution.
Various reload or capture functions can be selected to reload timers or capture a timer’s contents
triggered by an external signal or a selectable transition of toggle latch TxOTL.
The maximum resolution of the timers in module GPT1 is 400 ns (@ 20 MHz CPU clock). With its
maximum resolution of 200 ns (@ 20 MHz CPU clock) the GPT2 timers provide precise event
control and time measurement.
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to
prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time
interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up
procedure is always monitored. The software has to be designed to service the Watchdog Timer
before it overflows. If, due to hardware or software related failures, the software fails to do so, the
Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low
in order to allow external hardware components to reset.
The Watchdog Timer is a 16-bit timer, clocked with the CPU clock divided either by 2 or by 128. The
high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced
by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals
between 25 µs and 420 ms can be monitored (@ 20 MHz). The default Watchdog Timer interval
after reset is 6.55 ms (@ 20 MHz).
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