C165_96 Datasheet, PDF (32/283 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

10Jul97@15:33h
Memory Organization / C165/C163
3.1 Internal ROM
The C165/C163 may reserve an address area of variable size (depending on the version) for on-
chip mask-programmable ROM (organized as X _* 32) or Flash memory. The lower 32 KByte of the
on-chip ROM/Flash are referred to as “Internal ROM Area”. Internal ROM accesses are globally
enabled or disabled via bit ROMEN in register SYSCON. This bit is set during reset according to the
level on pin EA, or may be altered via software. If enabled, the internal ROM area occupies the
lower 32 KByte of either segment 0 or segment 1. This ROM mapping is controlled by bit ROMS1
in register SYSCON.
Note: The size of the internal ROM area is independent of the size of the actual implemented ROM.
Also devices with less than 32 KByte of ROM or with no ROM at all will have this 32 KByte
area occupied, if the ROM is enabled. Devices with larger ROMs provide the mapping option
only for the ROM area.
Devices with a ROM size above 32 KByte expand the ROM area from the middle of segment 1, ie.
starting at address 01’8000_H.
The internal ROM/Flash can be used for both code (instructions) and data (constants, tables, etc.)
storage.
Code fetches are always made on even byte addresses. The highest possible code storage location
in the internal ROM is either xx’xxFE_H for single word instructions, or xx’xxFC_H for double word
instructions. The respective location must contain a branch instruction (unconditional), because
sequential boundary crossing from internal ROM to external memory is not supported and causes
erroneous results.
Any word and byte data read accesses may use the indirect or long 16-bit addressing modes. There
is no short addressing mode for internal ROM operands. Any word data access is made to an even
byte address. The highest possible word data storage location in the internal ROM is xx’xxFE_H. For
PEC data transfers the internal ROM can be accessed independent of the contents of the DPP
registers via the PEC source and destination pointers.
The internal ROM is not provided for single bit storage, and therefore it is not bit addressable.
Note: The ‘x’ in the locations above depend on the available ROM/Flash memory and on the
mapping.
The internal ROM may be enabled, disabled or mapped into segment 0 or segment 1 under
software control. Chapter “System Programming” shows how to do this and reminds of the
precautions that must be taken in order to prevent the system from crashing.
Semiconductor Group
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