C165_96 Datasheet, PDF (222/283 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

10Jul97@15:33h
The Watchdog Timer (WDT) / C165/C163
Operation of the Watchdog Timer
The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT,
which is a non-bitaddressable read-only register. The operation of the Watchdog Timer is controlled
by its bitaddressable Watchdog Timer Control Register WDTCON. This register specifies the reload
value for the high byte of the timer, selects the input clock prescaling factor and provides a flag that
indicates a watchdog timer overflow.
WDTCON (FFAE_H / D7_H)
SFR
Reset Value: 000X_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTREL
WDT WDT
-
-
-
-
-
-
R IN
rw
-
-
-
-
-
-
r rw
Bit
WDTIN
WDTR
WDTREL
Function
Watchdog Timer Input Frequency Selection
‘0’: Input frequency is f_CPU / 2
‘1’: Input frequency is f_CPU / 128
Watchdog Timer Reset Indication Flag
Set by the watchdog timer on an overflow.
Cleared by a hardware reset or by the SRVWDT instruction.
Watchdog Timer Reload Value (for the high byte)
Note: The reset value will be 0002_H, if the reset was triggered by the watchdog timer (overflow). It
will be 0000_H otherwise.
After any software reset, external hardware reset (see note), or watchdog timer reset, the watchdog
timer is enabled and starts counting up from 0000_H with the frequency f_CPU/2. The input frequency
may be switched to f_CPU/128 by setting bit WDTIN. The watchdog timer can be disabled via the
instruction DISWDT (Disable Watchdog Timer). Instruction DISWDT is a protected 32-bit instruction
which will ONLY be executed during the time between a reset and execution of either the EINIT
(End of Initialization) or the SRVWDT (Service Watchdog Timer) instruction. Either one of these
instructions disables the execution of DISWDT.
When the watchdog timer is not disabled via instruction DISWDT, it will continue counting up, even
during Idle Mode. If it is not serviced via the instruction SRVWDT by the time the count reaches
FFFF_H the watchdog timer will overflow and cause an internal reset. This reset will pull the external
reset indication pin RSTOUT low. It differs from a software or external hardware reset in that bit
WDTR (Watchdog Timer Reset Indication Flag) of register WDTCON will be set. A hardware reset
or the SRVWDT instruction will clear this bit. Bit WDTR can be examined by software in order to
determine the cause of the reset.
A watchdog reset will also complete a running external bus cycle before starting the internal reset
sequence if this bus cycle does not use READY or samples READY active (low) after the
programmed waitstates. Otherwise the external bus cycle will be aborted.
Note: After a hardware reset that activates the Bootstrap Loader the watchdog timer will be
disabled.
Semiconductor Group
13-2