C165_96 Datasheet, PDF (175/283 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontrollers

The General Purpose Timer Units / C165/C163
Timer 6 in Counter Mode
Counter mode for the core timer T6 is selected by setting bit field T6M in register T6CON to ‘001_B’.
In counter mode timer T6 is clocked by a transition at the external input pin T6IN, which is an
alternate function of P5.12. The event causing an increment or decrement of the timer can be a
positive, a negative, or both a positive and a negative transition at this pin. Bit field T6I in control
register T6CON selects the triggering transition (see table below).
T6IN
=
T6EUD =
T6OUT =
P5.12
P5.10
P3.1
Figure 9-15
Block Diagram of Core Timer T6 in Counter Mode
x=6
GPT2 Core Timer T6 (Counter Mode) Input Edge Selection
T6I
000
001
010
011
1XX
Triggering Edge for Counter Increment / Decrement
None. Counter T6 is disabled
Positive transition (rising edge) on T6IN
Negative transition (falling edge) on T6IN
Any transition (rising or falling edge) on T6IN
Reserved. Do not use this combination
The maximum input frequency which is allowed in counter mode is f_CPU/8 (2.5 MHz @ f_CPU=20
MHz). To ensure that a transition of the count input signal which is applied to T6IN is correctly
recognized, its level should be held high or low for at least 4 f_CPU cycles before it changes.
Semiconductor Group
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