SDA9255 Datasheet, PDF (26/45 Pages) Siemens Semiconductor Group – SRC-Scan Rate Converter SDA9255

SDA 9255
SYNC_ST (every 40 ms) are indicated with „S“. The Ι²C-Bus status bits of the SDA 9255
(sub19_H, Bit 7; sub1E_H, Bit 7) reflect the state of the register values. If these bits are read
as ’0’ then the store command was sent, but the data aren’t made available yet. If these
bits are ’1’ then the data were made valid and a new write or read cycle can start. The
I²C-Bus status bits have to be checked before writing or reading new data, otherwise
data can be lost by overwriting.
After switching on the IC, all bits of the SDA 9255 are set to defined states. In particular:
Subaddress Default
Value
00_H
6F_H
01_H
56_H
02_H
68_H
03_H
23_H
04_H
10_H
05_H
30_H
06_H
50_H
07_H
not used
08_H
61_H
09_H
74_H
0A_H
8F_H
0B_H
94_H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Take Subaddress Default
Over
Value
S
0C_H
A2_H
S
0D_H
50_H
V
0E_H
2C_H
V
0F_H
81_H
V
10_H
00_H
V
11_H ... 18_H not used
V
19_H
1A_H ... 1D_H not used
V
1E_H
V
1F_H ... FE_H not used
V
FF_H
V
R/W Take
Over
R/W V
R/W S
R/W S
R/W S
R/W S
R/W
R
R/W
R
R/W
W
R/W:
R-Read Register, W-Write Register, R/W-Read and Write Register,
Take over: V-take over with V-Sync, S-take over with SYNC_ST
Semiconductor Group
24
1998-02-01