SDA9255 Datasheet, PDF (18/45 Pages) Siemens Semiconductor Group – SRC-Scan Rate Converter SDA9255

SDA 9255
2.4.3 VOUT, HOUT and HREF Signal Length
The length of the output synchronization signals (HOUT, VOUT) is fixed. The HOUT
signal is active high with a length of 32 system clocks (27.0 MHz) which corresponds to
a length of 1.185 µs. The VOUT signal is also active high with a length of 2 output lines.
So in case of PAL B/G the active high period of the VOUT lasts for 64 µs (see figure 13,
Timing for HOUT Signal and figure 14, Timing for VOUT Signal).
The HOUT signal of the SDA 9255 can be delayed by a fixed value of 172 system clocks
(27.0 MHz) by setting the HSODLY bit of subaddress 0F_H to ’1’(see description of
I²C Bus). The number of active pixels per line is constant 720 pixels. The HREF output
signal (pin 62) indicates the active part of the output lines. The length is also constant
(720 system clocks). During the vertical and horizontal blanking period this signal is low.
The timing is shown in figure 15 (see chapter 5.9, Timing for HREF Signal). The
chrominance output format is like the output format as described in chapter 1.
2.4.4 Output Synchronization Raster and Interlaced Output Signal
The output synchronization and data raster in 100/120 Hz mode can be set by the
MODESYNC register value (subaddress 01_H, see description of I²C Bus). In case of
MODE10050 = 1 (50/60 Hz pro-scan mode) this register value has no effect.
The interlaced signal INTERLACED (pin 59) is a control signal which may be used to
control an AC coupled vertical deflection unit. If the MODESYNC register value
(subaddress 01_H, see description of I²C Bus) is set to AABB mode, where field 2 and
3 have to be shifted down (MODESYNC = 10). For this the interlaced register INTL
(subaddress 0D_H and 0E_H, see description of I²C Bus) must be set to 0110. In figure
16 (see chapter 5.10, Example for INTERLACED Signal) an example for the INTL
register value is shown. Bit zero defines the output for the first field (field A); bit one
defines the output for the second field (field A); bit two defines the output of the third field
(field B); bit three defines the output of the fourth field (field B). So if the bit is set to zero
then the output is low and if the bit is set to one then the output is high. For DC coupled
vertical deflection the INTERLACED signal is not required.
Semiconductor Group
16
1998-02-01