SDA9255 Datasheet, PDF (11/45 Pages) Siemens Semiconductor Group – SRC-Scan Rate Converter SDA9255

SDA 9255
2
System Description
The device generates at its output an opportune sequence of 100/120 Hz fields (ααββ)
[50/60 Hz frames (αβ)] derived by processing the field A or B which is stored in one
internal field memory. The fields can be noise reduced and vertically zoomed.
Additionally the device generates a vertical sync pulse, a horizontal sync pulse and a
horizontal reference signal (horizontal active video output) in phase with the output data.
Furthermore an interlace signal for AC coupled vertical deflection is available.
2.1 Input Data Formats
The SDA 9255 accepts at the input side the following input format (relations of Y : (B-Y) :
(R-Y) : 4 : 1 : 1). The representation of the samples of the chrominance signal is
programmable as positive dual code (unsigned) or two's complement code (TWOIN,
TWOOUT, subaddress 00_H, see description of I²C Bus).
Data
Pin
SDA 9255
YIN7
Y₀₇
Y₁₇
Y₂₇
Y₃₇
YIN6
Y₀₆
Y₁₆
Y₂₆
Y₃₆
YIN5
Y₀₅
Y₁₅
Y₂₅
Y₃₅
YIN4
Y₀₄
Y₁₄
Y₂₄
Y₃₄
YIN3
Y₀₃
Y₁₃
Y₂₃
Y₃₃
YIN2
Y₀₂
Y₁₂
Y₂₂
Y₃₂
YIN1
Y₀₁
Y₁₁
Y₂₁
Y₃₁
YIN0
Y₀₀
Y₁₀
Y₂₀
Y₃₀
UVIN7
U₀₇
U₀₅
U₀₃
U₀₁
UVIN6
U₀₆
U₀₄
U₀₂
U₀₀
UVIN5
V₀₇
V₀₅
V₀₃
V₀₁
UVIN4
V₀₆
V₀₄
V₀₂
V₀₀
X_AB: X: signal component, A: sample number, B: bit number
The amplitude resolution for each input signal component is 8 Bit, the maximum clock
frequency is 27 MHz.
Semiconductor Group
9
1998-02-01