SDA9255 Datasheet, PDF (16/45 Pages) Siemens Semiconductor Group – SRC-Scan Rate Converter SDA9255

SDA 9255
2.4 Output Timing and Parameter
The SDA 9255 has six output signals:
HOUT
Pin 60
Horizontal synchronization signal - high
active
VOUT
Pin 61
Vertical synchronization signal - high active
HREF
Pin 62
Horizontal active video output
INTERLACED Pin 59
Interlace signal
YOUT0 ... 7 Pin 7, 6, 5, 4, 3, 1, 64, 63 Luminance output
UVOUT4 ... 7 Pin 13, 12, 11, 10
Chrominance output
There are different modes of output synchronization raster possible. The data output
signal of the SDA 9255 (YOUT, UVOUT and HREF) are fed to the digital-to-analog
converter. The timing of the output signals is given in figure 8 (see chapter 5.2, Output
Timing of the SDA 9255).
2.4.1 Number of Not Active Lines of Output Field
The register values NALOP and NAPOP are used to set the position of the active output
field on the screen. To do this the register value to align the not active lines (NALOP,
subaddress 0D_H, see description of I²C Bus) and the register value to align the not
active pixels (NAPOP, subaddress 0E_H, see description of I²C Bus) for the output
signal are available.
To change the vertical position of the picture on the screen the NALOP register can be
utilized. The NALOP register (not active lines for output) is used to adjust the number of
not active output lines in steps of two lines in case of 100/120 Hz interlaced and in steps
of four lines in case of 50/60 Hz proscan. To calculate the first active output line the
following formula can be used:
for MODE10050 = 0 ==> 100/120 Hz interlaced:
FAOPL = NALOP _* 2 + 3
for MODE10050 = 1 ==> 50/60 Hz proscan:
where
FAOPL = NALOP _* 4 + 5
FAOPL: The first active output line
NAL_OP: Register value
The maximum value for the first active line is 65 for 100/120 Hz and 129 for 50/60 Hz.
In figure 11 (see chapter 5.5, Example for Not Active Output Register) an example
for the setting of the NALOP register is shown. The synchronization output (HOUT,
Semiconductor Group
14
1998-02-01