SDA9255 Datasheet, PDF(12/45 Page) Siemens Semiconductor Group

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SDA9255 Datasheet, PDF (12/45 Pages) Siemens Semiconductor Group – SRC-Scan Rate Converter SDA9255

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SDA 9255

2.2 Output Data Formats

Data

YOUT7

YOUT6

YOUT5

YOUT4

YOUT3

YOUT2

YOUT1

YOUT0

UVOUT7

UVOUT6

UVOUT5

UVOUT4

Y07

Y17

Y27

Y37

Y06

Y16

Y26

Y36

Y05

Y15

Y25

Y35

Y04

Y14

Y24

Y34

Y03

Y13

Y23

Y33

Y02

Y12

Y22

Y32

Y01

Y11

Y21

Y31

Y00

Y10

Y20

Y30

U07

U05

U03

U01

U06

U04

U02

U00

V07

V05

V03

V01

V06

V04

V02

V00

XAB: X: signal component, A: sample number, B: bit number

2.3 Input Timing and Parameter

The SDA 9255 has five input signals:

HIN

Pin 23

VIN

Pin 22

SYNCEN Pin 30

YIN0 ... 7 Pin 42, 43, 44, 45, 46, 47 ,48, 49

UVIN4 ... 7 Pin 36, 37, 38, 39

Horizontal synchronization signal - low

or high active

Vertical synchronization signal - low or

high active

Enable signal for HIN and VIN signal,

low active

Luminance input

Chrominance input

The SDA 9255 includes a V-Sync delay block.This is implemented to make sure that the

field identification is working correctly. This is briefly described below.

The phase relation of the incoming horizontal synchronization signal (HIN) and the

incoming data for HSINP = 0 and VSINP = 0 is shown in figure 7 (see chapter 5.1, Input

Timing of the SDA 9255 (HSINP = 0)). The SDA 9255 needs the synchronization

enable input (SYNCEN) which is used to gate HIN and VIN. This is implemented for

frontends which are working with 13.5 MHz and a large output delay time for H-Sync and

Semiconductor Group

1998-02-01

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