HYB5117805BSJ-50- Datasheet, PDF (23/25 Pages) Siemens Semiconductor Group – 2M x 8 - Bit Dynamic RAM 2k Refresh

HYB5117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Read Cycle:
RAS
V _IH
V _IL
CAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
V _IH
V _IL
V _IH
V _IL
V _IH
V _IL
V _IH
V _IL
V _IH
V _IL
VOH
VOL
Write Cycle:
V _IH
WE
V _IL
OE
V _IH
V _IL
I/O
(Inputs)
V _IH
V _IL
I/O
V
(Outputs)
V
IH
IL
tRAS
tRP
tCSR
tCHR
tWRP
tWRH
tWRP
tWRH
tCP
tRSH
tCAS
tRAL
t t ASC
CAH
Column
tAA
tRCS
tCAC
tOEA
tASR
Row
tRRH
tRCH
tDZC
tDZO
tCLZ
tCDD
tODD
tOFF
tOEZ
Data Out
tWCS
tRWL
tCWL
tWCH
tDS
tDH
Data In
HI-Z
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
23