HYB514256B Datasheet, PDF (10/22 Pages) Siemens Semiconductor Group – 256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM

HYB 514256B/BL/BJ/BJL-50/-60/-70
256 K × 4-DRAM
Notes :
1) All voltages are referenced to V_SS .
2) I_CC1 , I_CC3 , I_CC4 , I_CC6 and I_CC7 depend on cycle rate.
3) I_CC1 and I_CC4 depend on output loading. Specified values are measured with the output open.
4) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles before proper device operation
is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles
instead of 8 RAS cycles are required.
5) V_IH (min.) and V_IL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between V_IH and V_IL.
6) Measured with a load equivalent to 2 TTL loads and 100 pF.
7) t_OFF (max.) and t_OEZ (max.) define the time at which the output achieves the open-circuit conditions and is not
referenced to output voltage levels.
8) Either t_RCH or t_RRH must be satisfied for a read cycle.
9) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-modify-write cycles.
10) t_WCS , t_RWD , t_CWD and t_AWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If t_WCS ≥ t_WCS (min.), the cycle is an early write cycle and data out pin will remain
open circuit (high impedance) through the entire cycle; if t_RWD ≥ t_RWD (min.), t_CWD ≥ t_CWD (min.) and t_AWD ≥ t_AWD
(min.), the cycle is a read-modify-write cycle and I/O will contain data read from the selected cell. If neither of
the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
11) Operation within the t_RCD (max.) limit insures that t_RAC (max.) can be met, t_RCD (max.) is specified as a reference
point only. If t_RCD is greater than the specified t_RCD (max.) limit, then access time is controlled by t_CAC .
12) Operation within the t_RAD (max.) limit insures that t_RAC (max.) can be met. t_RAD (max.) is specified as a reference
point only. If t_RAD is greater than the specified t_RAD (max.) limit, then access time is controlled by t_AA .
13) AC measurements assume t_T = 5ns.
14) Either t_DZC or t_DZO must be satisfied.
15) Either t_CDD or t_ODD must be satisfied.
Semiconductor Group
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