SM5K3 Datasheet, PDF (9/28 Pages) Sharp Electrionic Components – 4-Bit Single-Chip Microcomputers(Controllers With 10-Bit A/D Converter)

SM5K3/SM5K4/SM5K5
NOTES :
1. Applicable pins : P12, P13, P20-P23, P30-P33 (digital input
mode), P40-P43, P50-P53^∗1
2. Applicable pins : OSCIN, RESET, P10, P11
3. Applicable pins : RESET, P10-P13, P20-P23, P40-P43,
P50-P53 (digital input mode)^∗1
4. Applicable pins : P30-P33 (analog input mode)
5. Applicable pins : P00-P03 (high current port)
6. Applicable pins : P20-P23, P40-P43, P50-P53 (output mode)^∗1
7. No load (A/D conversion in stop)
8. A/D conversion in operation (operation enable)
9. A/D conversion in stop (operation disable)
∗1 In case of 32-pin SOP and 36-pin QFP.
( In case of 30-pin SDIP, P52 dose not exist. In case of
28-pin SOP, P50-P53 do not exist.)
SYSTEM CONFIGURATION
A Register and X Register
The A register (or accumulator : ACC) is a 4-bit
general purpose register. The register is mainly
used in conjunction with the ALU, C flag and RAM
to transfer numerical value and data to perform
various operations. The A register is also used to
transfer data between input and output pins.
The X register (or auxiliary accumulator) is a 4-bit
register and can be used as a temporary register.
It loads contents of the A register or its content is
transferred to the A register. When the table
reference instruction PAT is used, the X and A
registers load ROM data. A pair of A and X
registers can accommodate 8-bit data.
Arithmetic and Logic Unit (ALU) and
Carry Signal Cy
The ALU performs 4-bit parallel operation
4-bit data
4-bit data
ALU
Result of operation
Areg
c
Fig. 2 ALU
The ALU operates binary addition in conjunction
with RAM, C flag and A register. The carry signal
Cy is generated if a carry occurs during ALU
operation. Some instructions use Cy : ADC
instruction sets/clears the content of the C flag;
ADX instruction causes the program to skip the
next instruction. Note that Cy is the symbol for
carry signal and not for C flag.
3
0
A register
3
0
X register
EXAX instruction
Fig. 1 Data Transfer Example between
A Register and X Register
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