SM5K3 Datasheet, PDF (20/28 Pages) Sharp Electrionic Components – 4-Bit Single-Chip Microcomputers(Controllers With 10-Bit A/D Converter)

RA (Count register)
Bit 7
0
Bit i (i = 7 to 0)
Count clock input register
• Uses as counter part of timer/counter (count
clock input).
• Loads the content of RB to RA when the RA
overflows or when OUT command (BL = 0AH)
is executed.
RA←RB
• Loads the content of RA to X and A registers
upon execution of IN command (BL = 0AH).
(X, A)←RA
• Bit 7 = MSB, bit 0 = LSB
RB (Modulo register)
Bit 7
0
Bit i (i = 7 to 0)
Count initial value storage register
• Uses as modulo register of timer/counter
• Loads the content of RB to X and A registers
upon execution of
IN command (BL = 0BH) : X = upper bits,
A = lower bits.
(X, A)←RB
• Loads the contents of X and A registers to RB
upon execution of
OUT command (BL = 0BH) : X = upper bits,
A = lower bits.
RB←(X, A)
• Bit 7 : MSB, Bit 0 : LSB
RC (Timer control)
Bit 3
0
Bit 3
Starts up count of the timer.
0 | Stop
1 | Start
SM5K3/SM5K4/SM5K5
Bit 2 (Unused)
Bits 1 to 0
Select the source clock to the timer.
00 | fSYS (system clock)
01 | fSYS/2⁷
10 | fSYS/2¹⁵
11 | Falling edge input on P11 pin
RE (Interrupt mask flag)
Bit 3
0
Bit 3 (Unused)
Bit 2
Removes overflow interrupt from timer or standby
condition.
0 | Disable
1 | Enable
Bit 1
Interrupts on the falling edge of input from P11 pin,
or releases of standby mode by the Low input from
P11 pin.
0 | Disable
1 | Enable
Bit 0
Interrupts on the falling edge of input on P10 pin, or
releases of standby mode by the Low input from
P10 pin.
0 | Disable
1 | Enable
RF (P2 port direction register)
Bit 3
0
Bit i (i = 3 to 0)
Selection of input pin/output pin
0 | Set P2i pin to input.
1 | Set P2i pin to output.
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