SM5K3 Datasheet, PDF (16/28 Pages) Sharp Electrionic Components – 4-Bit Single-Chip Microcomputers(Controllers With 10-Bit A/D Converter)

SM5K3/SM5K4/SM5K5
• Usage of halt mode and stop mode
The system returns back to the normal operation
mode upon occurring of a standby mode releasing
condition. The halt mode should be used when the
system must enter and exit normal operation
frequently as in the case of key operation.
The halt mode should also be used to keep timers
that are operating from the internal clock, while in
the standby mode.
The stop mode further saves power than the halt
mode but requires slightly longer time to return to
the normal mode. Therefore, the stop mode should
be used when the system will not be required to
return to the normal mode in a short time.
Interrupt Feature
The interrupt block consists of mask flags (bits RE0,
RE1 and RE2), IME flag and interrupt request
handling circuit. Fig. 9 shows the configuration of the
interrupt block.
Mask flag (mode register RE)
RE2 RE1 RE0
Interrupt request flag
I FA
Stack register SR
Program counter PC
INT signal
I FB
Interrupt handling circuit
Interrupt enable flag
IME
(master enable flag)
I FT
Fig. 9 Interrupt Block Diagram
• Interrupt used with SM5K3/5K4/5K5
Interrupt event occurs on the falling edge of P10 or
P11 pin input, or the overflow at the timer. These
events set flags IFA, IFB and IFT respectively, that
then serve as interrupt request flag.
Table 4 shows interrupt handling priority level and
jump address.
INTERRUPT EVENT
(REQUEST FLAG)
Falling edge of input on P10 (IFA)
Falling edge of input on P11 (IFB)
Timer overflow (IFT)
Table 4 Interrupt Event Summary
JUMP ADDRESS
PAGE STEP
2
0
2
2
2
4
PRIORITY ORDER
1
2
3
INTERRUPT MASK FLAG
RE0
RE1
RE2
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