SM5K3 Datasheet, PDF(15/28 Page) Sharp Electrionic Components – 4-Bit Single-Chip Microcomputers(Controllers With 10-Bit A/D Converter)

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SM5K3 Datasheet, PDF (15/28 Pages) Sharp Electrionic Components – 4-Bit Single-Chip Microcomputers(Controllers With 10-Bit A/D Converter)

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SM5K3/SM5K4/SM5K5

Operation mode

Run HALT command

Normal

operation

HALT mode

release event

Run STOP command

STOP mode

release event

Standby mode

HALT mode

STOP mode

Fig. 8 Operation Shift of Program

â¢ Blocks stopped during standby mode

In the halt mode

The system clock generating circuit stops during

the halt mode, deactivating all the blocks driven by

the system clock. The main clock and dividers

remain active. This means that timers can be used

while in the halt mode. Both internal and external

clocks can be used as the count clock.

In the stop mode

The main clock and system clock stop upon

entering the stop mode. Therefore, only timers

using the external clock remain active.

â¢ Counters that the system retains during

standby mode

The contents that will be retained in the halt mode

will also be retained in the stop mode. These items

are shown in Table 3.

FLAG

IFA flag

IFB flag

IFT flag

IME flag

C flag

Table 3 System Contents Secured During Standby Mode

OUTPUT LATCH REGISTER/MODE REGISTER

A register

P0, P2, R3, P5

X register

R8, R9, RA, RB

BM, BL register

RC, RE, RF

OTHER

RAM

â¢ Releasing events of standby mode (6-type)

RELEASING EVENT

FLAG INT/EXT MASKABLE / NONMASKABLE

Reset input

External Nonmaskable

Low level input on P10 pin

IFA External Maskable

Low level input on P11 pin

IFB External Maskable

Low level input on P12 pin

External Nonmaskable

Low level input on P13 pin

External Nonmaskable

Timer overflow

IFT Internal Maskable

PRIORITY

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