SHARP_LH7A404 Datasheet, PDF (37/51 Pages) Sharp Electrionic Components – 32 BIT SYSTEM ON CHIP

32-Bit System-on-Chip
Synchronous Memory Controller Waveforms
Figure 10 shows the waveform and timing for a Syn-
chronous Burst Read (page already open). Figure 11
shows the waveform and timing for synchronous mem-
ory to activate a bank and Write.
tSCLK
SCLK
tOHXXX
SDRAMcmd
SA[13:0],
SBANK[1:0]
D[31:0]
READ
tOVB
tOVXXX
BANK,
tOVA ^COLUMN
tISD tIHD
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCSx.
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. nDQM is static LOW.
5. SDCKE is static HIGH.
DATA n
DATA n + 2
DATA n + 1
DATA n + 3
Figure 10. Synchronous Burst Read
LH7A404
LH7A404-13
tSCLK
SCLK
tOVC0
SDCKE
tOVXXX tOHXXX
SDRAMcmd
SA[13:0],
SBANK[1:0]
D[31:0]
ACTIVE
tOVA
tOVA
BANK,
ROW
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCSx.
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. Refer to the AC timing table.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. nDQM is static LOW.
Figure 11. Synchronous Bank Activate and Write
WRITE
BANK,
COLUMN
DATA
tOVD
tOHD
LH7A404-14
Advance Data Sheet
37