SHARP_LH7A404 Datasheet, PDF (33/51 Pages) Sharp Electrionic Components – 32 BIT SYSTEM ON CHIP

32-Bit System-on-Chip
LH7A404
AC Specifications (Commercial)
All signals described in Table 5 relate to transi-
tions following a reference clock signal. The illustra-
tion in Figure 6 represents all cases of these sets of
measurement parameters.
The reference clock signals in this design are:
• HCLK, the System Bus internal clock
• PCLK, the Peripheral Bus clock
• SSPCLK, the Synchronous Serial Port clock
• UARTCLK, the UART Interface clock
• LCDDCLK, the LCD Data clock from the
LCD Controller
• AC97CLK, the AC97 clock
• SCLK, the Synchronous Memory clock.
All signal transitions are measured from the 50%
point of the clock to the 50% point of the signal.
For outputs from the LH7A404, tOVXXX (e.g. tOVA)
represents the amount of time for the output to become
valid from the rising edge of the reference clock signal.
Maximum requirements for tOVXXX are shown in
Table 5.
The signal tOHXXX (e.g. tOHA) represents the
amount of time the output will be held valid following
the rising edge of the reference clock signal. Minimum
requirements for tOHXXX are listed in Table 5.
For inputs, tISXXX (e.g. tISD) represents the
amount of time the input signal must be valid before the
rising edge of the clock signal. Minimum requirements
for tISXXX are shown in Table 5.
The signal tIHXXX (e.g. tIHD) represents the
amount of time the output must be held valid following
the rising edge of the reference clock signal. Minimum
requirements are shown in Table 5.
REFERENCE
CLOCK
tOVXXX
tOHXXX
SIGNAL
A[27:0]
D[31:0]
nCS[7:0]
nWE[3:0]
nBLE[3:0]
nOE
OUTPUT
SIGNAL (O)
tISXXX tIHXXX
INPUT
SIGNAL (I)
Figure 6. LH7A404 Signal Timing
Table 5. AC Signal Characteristics
TYPE LOAD DRIVE SYMBOL
MIN. MAX.
DESCRIPTION
Output
Output
Input
Output
Output
Output
Output
ASYNCHRONOUS MEMORY INTERFACE SIGNALS
50 pF 8 mA
tOVA
tOHA
8 ns Address Valid
0 ns
Address Hold
50 pF 8 mA
tOVD
tOHD
6 ns Data Valid
2 ns
Data Hold
tISD
2 ns
Data Setup
tIHD
0 ns
Data Hold
30 pF 8 mA
tOVCS
tOHCS
8 ns Chip Select Valid
0 ns
Chip Select Hold
30 pF 8 mA
tOVWE
tOHWE
8 ns Write Enable Valid
0 ns
Write Enable Hold
30 pF 8 mA
tOVBLE
tOHBLE
8 ns Byte Lane Enable Valid
0 ns
Byte Lane Enable Hold
30 pF 8 mA
tOVOE
tOHOE
8 ns Ouput Enable Valid
0 ns
Ouput Enable Hold
LH7A404-9
Advance Data Sheet
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