SHARP_LH7A404 Datasheet, PDF (21/51 Pages) Sharp Electrionic Components – 32 BIT SYSTEM ON CHIP

32-Bit System-on-Chip
LH7A404
AMBA APB BUS
The AMBA APB bus is a low speed 32-bit-wide
peripheral data bus. The speed of the APB bus is
selected by dividing the clock speed of the AHB bus by
two, four, or eight.
EXTERNAL BUS INTERFACE (EBI)
The External Bus Interface (EBI) provides a 32-bit
wide, high speed gateway to external memory devices.
The supported memory devices include:
• Asynchronous RAM/ROM/Flash
• Synchronous DRAM/Flash
• PCMCIA interfaces
• Compact Flash interfaces.
The EBI can be controlled by either the Asynchro-
nous Memory Controller or Synchronous Memory Con-
troller. There is an arbiter on the EBI input, with priority
given to the Synchronous Memory Controller interface.
LCD BUS
The LCD controller has its own local memory bus
that connects it to the system’s embedded memory and
external SDRAM. The function of this local data bus is
to allow the LCD controller to perform its video refresh
function without congesting the main AHB bus. This
leads to better system performance and lower power
consumption. There is an arbiter on both the embed-
ded memory and the synchronous memory controller.
In both cases the LCD bus is given priority.
DMA BUSES
The LH7A404 has a DMA system which connects
the higher speed/higher data volume APB peripherals
(MMC, USB and AC97) to the AHB bus. This enables
the efficient transfer of data between these peripherals
and external memory without the intervention of the
ARM922T core. The DMA engine does not support
memory-to-memory transfers.
USB HOST CONTROLLER DMA BUS
The USB Host Controller has its own DMA control-
ler. It acts as another bus master on the AHB bus. It
does not interact with the non-USB DMA controller
except in bus arbritration.
Memory Map
The LH7A404 system has a 32-bit-wide address bus,
allowing addressing up to 4GB of memory. This mem-
ory space is subdivided into a number of memory
banks, shown in Figure 4. Four of these banks (each
256MB) are allocated to the Synchronous Memory
Controller. Eight banks (each 256MB) are allocated to
the Asynchronous Memory Controller. Two of these
eight banks are designed for PCMCIA systems. Part of
the remaining memory space is allocated to the embed-
ded SRAM, and to the control registers of the AHB and
APB. The rest of the memory space is not used.
The LH7A404 can boot from either synchronous or
asynchronous ROM/Flash. The selection is determined
by the value of the MEDCHG pin at power-on reset as
shown in Table 4. When booting from synchronous
memory, bank 4 (nSCS3) is mapped into memory loca-
tion zero. When booting from asynchronous memory,
memory bank 0 (nSCS0) is mapped into memory loca-
tion zero.
Figure 4 shows the memory map of the LH7A404
system for the two boot modes.
Once the LH7A404 has booted, the boot code can
configure the ARM922T MMU to remap the low mem-
ory space to a location in RAM. This allows the user to
set the interrupt vector table.
Table 4. Boot Modes
BOOT MODES
LATCHED
BOOT-
WIDTH1
LATCHED
BOOT-
WIDTH0
LATCHED
MEDCHG
8-bit ROM
0
0
0
16-bit ROM
0
1
0
32-bit ROM
1
0
0
32-bit ROM
1
1
0
16-bit SFlash
(Initializes Mode Register)
0
0
1
16-bit SROM
(Initializes Mode Register)
0
1
1
32-bit SFlash
(Initializes Mode Register)
1
0
1
32-bit SROM
(Initializes Mode Register)
1
1
1
Advance Data Sheet
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