SHARP_LH7A404 Datasheet, PDF (26/51 Pages) Sharp Electrionic Components – 32 BIT SYSTEM ON CHIP

LH7A404
32-Bit System-on-Chip
The DMA features:
• Two dedicated channels for M2M and external M2P/
P2M
• Ten fully independent, programmable DMA control-
ler internal M2P/P2M channels (5 Tx and 5 Rx)
• Channels assignable to one of a number of different
peripherals
• Independent source and destination address regis-
ters. Source and destination can be programmed to
auto-increment or not auto-increment for M2M chan-
nels
• Two buffer descriptors per M2P and M2M channel to
avoid potential data under/over-flow due to software
introduced latency. A buffer refers to the area in sys-
tem memory that is characterized by a buffer
descriptor, ie., a start address and the length of the
buffer in bytes
• No AMBA wrapping bursts for DMA channels; only
incrementing bursts are supported
• Buffer size independent of the peripheral’s packet
size for the internal M2P channels. Transfers can
automatically switch between buffers
• Maskable interrupt generation
• Internal arbitration between DMA channels, plus
support for an AHB bus arbiter
• DMA data transfer sizes, byte, word and quad-word
data transfers are supported using a 16-byte data
bay. Maximum data transfer size per M2M channel
is programmable
• Per-channel clock gating reducing power in chan-
nels that have not been enabled by software. See
the ‘Clock and State Controller’ section.
A set of control and status registers are available to
the system processor for setting up DMA operations
and monitoring their status. System interrupts are gen-
erated when any/all of the DMA channels wish to
inform the processor to update the buffer descriptor.
The DMA controller can service 10 out of 20 possible
peripherals using the ten DMA channels, each with its
own peripheral DMA bus capable of simultaneously
transferring data in both directions.
The SD/MMC, UART1/2/3, USB Device, and USB
Host peripherals can each use two DMA channels, one
for transmit and one for receive. The AAC peripheral
can use six DMA channels (three transmit and three
receive) to allow different sample frequency data
queues to be handled with low software overheads.
The DMA controller includes an M2M transfer fea-
ture allowing block moves of data from one memory
address space to another with minimum of program
effort and time. An M2M software trigger capability is
provided. The DMA controller can also fill a block of
memory with data from a single location.
The DMA controller’s M2M channels can also be
used in M2P/P2M mode. A set of external handshake
signals, DREQ, DACK and TC/DEOT are provided for
each of two M2M channels.
DREQ (input) can be programmed edge or level
active, and active HIGH or LOW. The peripheral may
hold DREQ active for the duration of the block transfers
or may assert/deassert on each transfer.
DACK (output) can be programmed active HIGH or
LOW. DACK will assert and return to de-asserted with
each Read or Write, the timing coinciding with nOE or
nWE from the EBI.
TC/DEOT is a bidirectional signal with programma-
ble direction and active polarity. When configured as an
Output, the DMA will assert Terminal Count (TC) on the
final transfer to coincide with the DACK, typically when
the byte count has expired. When configured as an
Input, the peripheral must assert DEOT concurrent with
DREQ for the final transfer in the block.
Transfer is terminated when DEOT is asserted by
the external peripheral or when the byte count expires,
whichever occurs first. Status bits indicate if the actual
byte count is equal to the programmed limit, and if the
count was terminated by peripheral asserting DEOT.
Terminating the transfer causes a DMA interrupt on
that channel and rollover to the ‘other’ buffer if so con-
figured.
For byte- or word-wide peripherals, the DMA is pro-
grammed to request byte- or word-wide AHB transfers
respectively. The DMA does not issue an AHB HREQ
for a transfer until it has DREQ asserted after a DACK
for the previous transfer; and the previous transfer has
been asserted for the duration of the programmed wait
states in the SMC (and possibly DREQ is sampled in
the cycle DACK is deasserted).
USB Device
The features of the USB are:
• Fully compliant to USB 1.1 specification
• Provides a high-level interface that shields the firm-
ware from USB protocol details
• Compatible with both OpenHCI and Intel UHCI
standards
• Supports full-speed (12 Mbps) functions
• Supports Suspend and Resume signalling.
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