SHARP_LH7A404 Datasheet, PDF (35/51 Pages) Sharp Electrionic Components – 32 BIT SYSTEM ON CHIP

32-Bit System-on-Chip
LH7A404
Asynchronous Memory
Controller Waveforms
Figure 7 shows the waveform and timing for an
external asynchronous memory Write. Figure 8 shows
the waveform and timing for an external asynchronous
memory Read, with one wait state. Figure 9 shows the
waveform and timing for an external asynchronous
memory Read, with two wait states.
HCLK
A[27:0]
(NOTE 1)
D[31:0]
nCS(X)
tOVA
ADDRESS
tOVD
DATA
tOHA
tOHD
tOVD
nBLE[3:0], nWE
tOVCS
NOTES:
1. A[24:0] when SCI used.
2. All signal transitions are measured from the
50% point of the clock to the 50% point of the signal.
tOVBLE, tOVWE
tOHBLE, tOHWE
Figure 7. External Asynchronous Memory Write
tOHCS
1 WAIT STATE
DATA READ
HCLK
A[25:0]
D[31:0]
nCSx
tOVA
ADDRESS
DATA
tISD
tOHA
tIHD
tOVCS
nOE
tOHCS
tOVOE
NOTE: All signal transitions are measured from the
50% point of the clock to the 50% point of the signal.
tOHOE
Figure 8. External Asynchronous Memory Read, One Wait State
Advance Data Sheet
LH7A404-10
LH7A404-11
35