SHARP_LH7A404 Datasheet, PDF (20/51 Pages) Sharp Electrionic Components – 32 BIT SYSTEM ON CHIP

LH7A404
32-Bit System-on-Chip
Power Modes
The LH7A404 has three operational states: Run,
Halt, and Standby. During Run all clocks are hardware
enabled and the processor is clocked. In the Halt mode
the device is functioning, but the processor clock is
halted while it waits for an event such as a key press.
Standby equates to the computer being switched ‘off’,
i.e. no display (LCD disabled) and the main oscillator is
shut down.
Reset Modes
Three external signals can generate resets to the
LH7A404: nPOR (power on reset), nPWRFL (power
failure) and nURESET (user reset). If any of these are
active, a system reset is internally generated. An nPOR
reset performs a full system reset. The nPWRFL and
nURESET resets perform a full system reset except for
the SDRAM refresh control, SDRAM Global Configura-
tion, SDRAM Device Configuration, and the RTC
peripheral registers. The SDRAM controller issues a
self-refresh command to external SDRAM before the
system enters an nPWRFL and nURESET reset. This
allows the system to maintain its Real Time Clock and
SDRAM contents. At reset termination, the chip enters
Standby mode. Once in the Run mode the PWRSR reg-
ister can be interrogated to determine the nature of the
reset and the trigger source, after which software can
then take appropriate actions.
Data Paths
The data paths in the LH7A404 are:
• The AMBA AHB bus
• The AMBA APB bus
• The External Bus Interface
• The LCD AHB bus
• The DMA busses.
AMBA AHB BUS
The Advanced Microprocessor Bus Architecture
AHB (AMBA AHB) is a high speed 32-bit-wide data bus.
The AMBA AHB is for high-performance, high-clock-fre-
quency system modules.
Peripherals with high bandwidth requirements are
connected to the LH7A404 core processor using the
AHB bus, Boot ROM, Vectored Interrupt Controllers,
and USB Device. These include the external and inter-
nal memory interfaces, the LCD registers, palette RAM
and the bridge to the Advanced Peripheral Bus (APB)
interface. The APB Bridge transparently converts the
AHB access into the slower speed APB accesses. All
control registers for the APB peripherals are pro-
grammed using the AHB-to-APB bridge interface. The
main AHB data and address lines are configured using
a multiplexed bus. This removes the need for tri-state
buffers and bus holders and simplifies bus arbitration.
14.7456 MHz
MAIN OSC.
32.768 kHz
RTC OSC.
STATE CONTROLLER
DIVIDE REGISTER
FCLK
HCLK
(TO PROCESSOR CORE)
HCLK
/2, /4, /8
PCLKs
Figure 3. Clock and State Controller Block Diagram
LH7A404-6
20
Advance Data Sheet