GS6152 Datasheet, PDF (61/80 Pages) Semtech Corporation – Multi-Rate 6G UHD-SDI

Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name Parameter Name
PRBSGEN_DATASEL
PRBSGEN_DIV
PRBSGEN_START
PRBSGEN_EXT_CLK
PRBSGEN_PHASE
22_h PRBS_GEN_CTRL
PRBSGEN_CLKSEL
PRBSGEN_RATESEL
PRBSGEN_VCO_
POWERDOWN
PRBSGEN_ENABLE
Bit
Slice
R/W
Reset
Value
Description
14:14 RW
13:12 RW
11:11 RW
10:10 RW
9:8 RW
7:7 RW
6:2 RW
1:1 RW
0:0 RW
Determines the DFT data output.
1_h 00_b: Clock
01_b: PRBS7 data
Divide ratio for the DFT clock.
00_b: divide by 1
0_h 01_b: divide by 2
10_b: divide by 4
11_b: divide by 8
0_h
When toggled HIGH then LOW starts the
internal PRBS7 data source.
Selects the source for the DFT clock.
0_h 00_b: Internally generated clock
01_b: External clock
Controls the phase of the internally
generated DFT clock.
2_h
00_b: 0 degree phase
01_b: 90 degree phase
10_b: 180 degree phase
11_b: 270 degree phase
Determines the source clock used by the
PRBS generator when PRBSGEN_EXT = 0
0_h ^{(internally generated clock).}
00_b: DFT VCO clock
01_b: CDR clock
One-hot encoded rate indicator for the
dividers in PRBS generator circuit.
00001_b: MADI
2_h 00010_b: SD
00100_b: HD
01000_b: 3G
10000_b: 6G
When HIGH, causes the open-loop PRBSGEN
VCO to be shut off even if
0_{h PRBSGEN_ENABLE = 1.}
Has no effect when PRBSGEN_ENABLE = 0.
When HIGH, the PRBS7 generator circuit is
enabled.
0_{h Must be enabled when using any feature in}
the PRBS_GEN_CTRL register.
GS6152
Final Data Sheet
PDS-060984
Rev.2
July 2015
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