GS6152 Datasheet, PDF (35/80 Pages) Semtech Corporation – Multi-Rate 6G UHD-SDI

Table 4-8: GSPI Timing Parameters (Continued)
Parameter
Equivalent
Symbol
SCLK
Cycles
Min
Typ
Max
(at 27MHz)
Inter-command delay time
t_cmd
4
120.0
—
—
Inter-command delay time
(after GSPI configuration write)
t_{cmd_GSPI_}
conf¹
5
162.0
—
—
SDO after SCLK falling edge
t₆
—
—
7.5
CS high after final SCLK falling
edge
t₇
0.0
—
—
Input data hold time
t₈
1.0
—
—
CS high time
t₉
57.0
—
—
SDIN to SDOUT combinational
delay
—
—
5.0
Max. chips daisy chained at
max SCLK frequency
When host clocks in SDOUT
—
—
1
Max. frequency for 32
daisy-chained devices
data on rising edge of SCLK
—
—
2.1
Max. chips daisy-chained at
max. SCLK frequency
When host clocks in SDOUT
—
—
3
Max. frequency for 32
daisy-chained devices
data on falling edge of SCLK
—
—
2.2
Note:
1. t_{cmd_GSPI_conf} inter-command delay must be used whenever modifying HOST_CONFIG register at address 0x00
4.11.7 Single Read/Write Access
Single read/write access timing for the GSPI interface is shown in Figure 4-11 to
Figure 4-15.
When performing a single read or write access, one Data Word is read from/written to
the device per access. Each access is a minimum of 32-bits long, consisting of a
Command Word and a single Data Word. The read or write cycle begins with a
high-to-low transition of the CS pin. The read or write access is terminated by a
low-to-high transition of the CS pin.
The maximum interface clock rate is 27MHz and the inter-command delay time
indicated in the figures as t_cmd, is a minimum of 4 SCLK clock cycles. After modifying
values in HOST_CONFIG, the inter-command delay time, t_{cmd_GSPI_config}, is a minimum
of 5 SCLK clock cycles.
For read access, the time from the last bit of the Command Word to the start of the data
output, as defined by t₅, corresponds to no less than 5 SCLK clock cycles at 27MHz.
Units
ns
ns
ns
ns
ns
ns
ns
GS6152
chips
MHz
GS6152
chips
MHz
GS6152
Final Data Sheet
PDS-060984
Rev.2
July 2015
www.semtech.com
35 of 80
Semtech
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