GS6152 Datasheet, PDF (46/80 Pages) Semtech Corporation – Multi-Rate 6G UHD-SDI

It is important to note that while the on-chip VCO is trimmed to within 0.5% of SMPTE
data rates, VT variation may extend the deviation from exact SMPTE data rates. If
frequency precision is required it is recommended to use the external pins or retimed
clock to provide a clock reference for the PRBS generator. The selection of reference
clock for the PRBS generator is done through programming the bits as in Table 4-11.
Table 4-11: Reference Clock for the PRBS Generator
PRBS_EXT_CLK
0
0
1
PRBSGEN_CLKSEL
0
1
X
Clock Reference
On-chip PRBSGEN VCO
CDR re-timed clock
Clock reference pins (GS6152 only)
To enable the PRBS generator the PRBSGEN_ENABLE bit of the PRBS_GEN_CTRL register
must be set high. The PRBS bit stream starts on the falling edge of the PRBSGEN_START
bit. To output the PRBS generator on the trace driver output the OUTPUT_PRBS_DATA0
and/or OUTPUT_PRBS_DATA1 bits of the DRIVER_CONTROL_REG_0 register need to be
set to 1.
The PRBS generator can also output a clock instead of a PRBS7 bit stream. The clock
output is selected by setting the PRBSGEN_DATASEL bit of the PRBS_GEN_CTRL register
to 0. Both the PRBS7 generator and clock output can have their frequency of operation
divided by 1, 2, 4 or 8 by setting the PRBSGEN_DIV bits of the PRBS_GEN_CTRL register,
down to an output data rate of 125Mb/s.
Additionally, when either the On-Chip PRBSGEN VCO or the re-timed clock is used as the
clock reference for the PRBS generator the phase of the output can be coarsely adjusted
to 0, 90, 180 or 270^º by programming PRBSGEN_PHASE bit of the PRBS_GEN_CTRL
register.
Note: It is recommended that the AUTO_LOS_MUTE_ENABLE and
AUTO_PWRDN_DISABLE parameters are set to disabled when the PRBS generator uses
the on-chip PRBSGEN VCO or the external clock pins to avoid muting the (PRBS
generator) output upon loss of signal on the input pins.
GS6152
Final Data Sheet
PDS-060984
Rev.2
July 2015
www.semtech.com
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