SX8724C Datasheet, PDF (23/67 Pages) Semtech Corporation – ZoomingADC for sensing data acquisition

SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
7.5 Second Stage Programmable Gain Amplifier (PGA2)
The second PGA has a finer gain and offset tuning capability, as shown in Table 12. The VD2 voltage at the output of
PGA2 is given by:
V_D2 = GD₂ ⋅V_D1 − GDoff₂ ⋅ S ⋅V_REF [V ]
Equation 6
where GD2 and GDOFF2 are respectively the gain and offset of PGA2 (in V/V). These are controlled with the words
Pga2Gain[1:0] and Pga2Offset[3:0].
Table 12. PGA2 gain and offset settings
Pga2Gain bitfield
(RegACCfg2[5:4])
00
01
10
11
PGA2 gain [V/V]
GD2 [V/V]
1
2
5
10
Pga2Offset bitfield
(RegACCfg2[3:0])
0000
0001
0010
0011
0100
0101
1000
1001
1010
1011
1100
1101
PGA2 offset
GDOFF2 [V/V]
0
+0.2
+0.4
+0.6
+0.8
+1
0
-0.2
-0.4
-0.6
-0.8
-1.0
7.6 Third Stage Programmable Gain Amplifier (PGA3)
The finest gain and offset tuning is performed with the third and last PGA stage, according to the coding of Table 13.
Table 13. PGA3 Gain and Offset Settings
Pga3Gain bitfield
(RegACCfg3[6:0])
0000000
0000001
...
0000110
...
0001100
0010000
...
0100000
PGA3 Gain
GD3 [V/V]
0
1/12 (=0.083)
...
6/12
...
12/12
16/12
...
32/12
Pga3Offset bitfield
(RegACCfg4[6:0])
0000000
0000001
...
0010000
...
0100000
...
0111111
1000000
PGA3 Offset
GDOFF3 [V/V]
0
+1/12 (=0.083)
+16/12
...
32/12
...
+63/12 (=+5.25)
0
Revision 1.01
© Semtech
January 2011
Page 23
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