SX8724C Datasheet, PDF (22/67 Pages) Semtech Corporation – ZoomingADC for sensing data acquisition

ADVANCED COMMUNICATIONS & SENSING
SX8724C
ZoomingADC for sensing data acquisition
DATASHEET
Table 9. Analog Input Selection
Amux
(RegACCfg5[5:1])
Sign S = 1
00x01
00x10
00x11
10000
10001
10010
10011
10100
10101
10110
10111
VINP
AC3
AC5
AC7
AC0(VSS)
AC1(VREF)
AC2
AC3
AC4
AC5
AC6
AC7
VINN
AC2
AC4
AC6
AC0(VSS)
Amux
(RegACCfg5[5:1])
Sign S = -1
01x01
01x10
01x11
11000
11001
11010
11011
11100
11101
11110
11111
VINP
AC2
AC4
AC6
AC0(VSS)
VINN
AC3
AC5
AC7
AC0(VSS)
AC1(VREF)
AC2
AC3
AC4
AC5
AC6
AC7
Similarly, the reference voltage is chosen among two differential channels (VREF = VBATT-VSS, VREF = VBG-VSS or VREF =
VREF,IN-VSS) as shown in Table 10. The selection bit is Vmux. The reference inputs VREFP and VREFN (common-mode) can
be up to the power supply range.
Table 10. Analog reference Input Selection
Vmux
(RegACCfg5[0])
VREFP
VREFN
0
VREF = VBATT
VSS
1
VREF = VBG or VREF,IN¹
VSS
1. External voltage reference on D1 GPIO pin. See section 6.3 on page 14 about
GPIO and “RegMode[0x70]” on page 46.
7.4 First Stage Programmable Gain Amplifier (PGA1)
The first stage can have a buffer function (unity gain) or provide a gain of 10 (see Table 11). The voltage VD1 at the
output of PGA1 is:
V_D1 = GD₁ ⋅V_IN [V ]
Equation 5
where GD1 is the gain of PGA1 (in V/V) controlled with the Pga1Gain bit.
Table 11. PGA1 gain settings
Pga1Gain bit
(RegACCfg3[7])
0
1
PGA1 gain [V/V]
GD1 [V/V]
1
10
Revision 1.01
© Semtech
January 2011
Page 22
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