SX8724C Datasheet, PDF (10/67 Pages) Semtech Corporation – ZoomingADC for sensing data acquisition

ADVANCED COMMUNICATIONS & SENSING
2.1.2 I2C interface timings
Table 6. Digital interface
Parameter
Symbol
I2C TIMING SPECIFICATIONS Note 1
SCL clock frequency
SCL timeout ( optional mode ) Note 2
SCL Low Pulsewidth
SCL High Pulsewidth
Start Condition Hold Time
Data Setup Time
fSCL
tSCLTO
tL
tH
tSCH
tDS
STANDARD-MODE
Min
Typ
0
35
4.7
4.0
0.6
250
Data Hold Time
tDH
0
Note 4
Setup Time for Repeated Start
tRSU
4.7
Stop Condition Setup Time
tPSU
4.0
Bus Free Time between a STOP
Condition and a START Condition
tBF
4.7
Pulsewidth of Spike Suppressed
tSUP
100
Capacitive load for each bus line
CB
Noise margin at the LOW level for each
connected device (including
VnL
hysteresis)
0.1VBATT
Noise margin at the HIGH level for each
connected device (including
VnH
hysteresis)
0.2VBATT
SX8724C
ZoomingADC for sensing data acquisition
DATASHEET
FAST-MODE
Max
Min
Typ
Unit
Max
100
0
35
1.3
0.6
0.6
100
Note 3
400
kHz
ms
μs
μs
μs
ns
3.45
0
0.9
μs
0.6
μs
0.6
μs
1.3
μs
100
ns
400
400
pF
0.1VBATT
V
0.2VBATT
V
(1) All timings specifications are referred to VILmin and VIHmax voltage levels defined for the SCL and SDA pins.
(2) The digital interface is reset if the SCL is low more than tSCLTO duration. This is the default mode at startup. The timeout can be disabled by
register setting.
(3) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system.
(4) The device internally provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(5) Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times according to Table 6 are allowed.
Revision 1.01
© Semtech
January 2011
Page 10
www.semtech.com/products/