SX8724C Datasheet, PDF (20/67 Pages) Semtech Corporation – ZoomingADC for sensing data acquisition

SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
7.1.3 PGA & ADC Enabling
Depending on the application objectives, the user may enable or bypass each PGA stage. This is done according to the
word Enable and the coding given in Table 7. To reduce power dissipation, the ADC can also be inactivated while idle.
Table 7. ADC and PGA Enabling
Enable
(RegACCfg1[3:0])
XXX0
XXX1
XX0X
XX1X
X0XX
X1XX
0XXX
1XXX
Block
ADC disabled
ADC enabled
PGA1 disabled
PGA1 enabled
PGA2 disabled
PGA2 enabled
PGA3 disabled
PGA3 enabled
7.2 ZoomingADC Registers
The system has a bank of eight 8-bit registers: six registers are used to configure the acquisition chain (RegAcCfg0 to
RegAcCfg5), and two registers are used to store the output code of the analog-to-digital conversion (RegAcOutMsb &
Lsb).
Table 8. Periferal Registers to Configure the Acquisition Chain (AC) and to Store the Analog-to-Digital
Conversion (ADC) Result
Bit position
Register Name
7
6
5
4
3
2
1
0
RegACOutLsb
Out[7:0]
Note 1
RegACOutMsb
Out[15:8]
RegACCfg0
Default values:
RegACCfg1
Default value:
RegACCfg2
Default value:
RegACCfg3
Default value:
RegACCfg4
Default value:
RegACCfg5
Default value:
Start
0, Note 2
SetNelconv
01, Note 3
IbAmpAdc
11, Note 7
SetFs
00, Note 10
Pga1Gain
0, Note 11
-
0
Busy
0, Note 16
Def
0, Note 17
IbAmpPga
11, Note 8
Pga2Gain
00, Note 12
SetOsr
010, Note 4
Pga3Gain
0001100, Note 13
Pga3Offset
0000000, Note 15
Amux
00000, Note 18
Continuous
0, Note 5
Enable
0000, Note 9
Pga2Offset
0000, Note 14
-
0, Note 6
Vmux
0, Note 19
(r = read; w = write; rw = read & write)
(1) Out: (r) digital output code of the analog-to-digital converter. (MSB = Out[15])
(2) Start: (w) setting this bit triggers a single conversion (after the current one is finished). This bit always reads back 0.
Revision 1.01
© Semtech
January 2011
Page 20
www.semtech.com/products/