SX8724C Datasheet, PDF (21/67 Pages) Semtech Corporation – ZoomingADC for sensing data acquisition

SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
(3) SetNelconv: (rw) sets the number of elementary conversions to 2^{(SetNelconv[1:0])}. To compensate for offsets, the input signal is chopped
between elementary conversions (1,2,4,8).
(4) SetOsr: (rw) sets the over-sampling rate (OSR) of an elementary conversion to 2^{(3+SetOsr[2:0])}. OSR = 8, 16, 32, ..., 512, 1024.
(5) Continuous: (rw) setting this bit starts a conversion. When this bis is 1, A new conversion will automatically begin directly when the previ-
ous one is finished.
(6) Reserved
(7) IbAmpAdc: (rw) sets the bias current in the ADC to 0.25 x (1+ IbAmpAdc[1:0]) of the normal operation current (25, 50, 75 or 100% of nom-
inal current). To be used for low-power, low-speed operation.
(8) IbAmpPga: (rw) sets the bias current in the PGAs to 0.25 x (1+IbAmpPga[1:0]) of the normal operation current (25, 50, 75 or 100% of nom-
inal current). To be used for low-power, low-speed operation.
(9) Enable: (rw) enables the ADC modulator (bit 0) and the different stages of the PGAs (PGAi by bit i=1,2,3). PGA stages that are disabled are
bypassed.
(10) SetFs: (rw) These bits set the over sampling frequency of the acquisition chain. Expressed as a fraction of the oscillator frequency, the
sampling frequency is given as: 11 ' 500 kHz, 10 ' 250 kHz, 01 ' 125 kHz, 00 ' 62.5 kHz.
(11) Pga1Gain: (rw) sets the gain of the first stage: 0 ' 1, 1 ' 10.
(12) Pga2Gain: (rw) sets the gain of the second stage: 00 ' 1, 01 ' 2, 10 ' 5, 11 ' 10.
(13) Pga3Gain: (rw) sets the gain of the third stage to Pga3Gain[6:0] 1/12.
(14) Pga2Offset: (rw) sets the offset of the second stage between -1 and +1, with increments of 0.2. The MSB gives the sign (0 positive, 1 neg-
ative); amplitude is coded with the bits Pga2Offset[5:0].
(15) Pga3Offset: (rw) sets the offset of the third stage between -5.25 and +5.25, with increments of 1/12. The MSB gives the sign (0 positive, 1
negative); amplitude is coded with the bits Pga3Offset[5:0].
(16) Busy: (r) set to 1 if a conversion is running.
(17) Def: (w) sets all values to their defaults (PGA disabled, max speed, nominal modulator bias current, 2 elementary conversions, over-sam-
pling rate of 32) and starts a new conversion without waiting the end of the preceding one.
(18) Amux(4:0): (rw) Amux[4] sets the mode (0 ' differential inputs, 1 ' single ended inputs with A0= common reference) Amux[3] sets the sign
(0 ' straight, 1' cross) Amux[2:0] sets the channel.
(19) Vmux: (rw) sets the differential reference channel (0 ' VBATT_, 1 ' VREF).
7.3 Input Multiplexers (AMUX and VMUX)
The ZoomingADC has analog inputs AC0 to AC7 and reference inputs. Let us first define the differential input voltage
VIN and reference voltage VREF,ADC respectively as:
V_IN = V_INP −V_INN [V]
Equation 3
V_REF = V_REFP −V_REFN [V ]
Equation 4
As shown in Table 9, the inputs can be configured in two ways: either as 4 differential channels (VIN1= AC1 - AC0,... , VIN4
= AC7 - AC6), or AC0 can be used as a common reference, providing 7 signal paths all referred to AC0. The control word
for the analog input selection is Amux. Notice that the Amux bit 4 controls the sign of the input voltage.
Amux
(RegACCfg5[5:1])
Sign S = 1
00x00
VINP
AC1(VREF)
Table 9. Analog Input Selection
VINN
AC0(VSS)
Amux
(RegACCfg5[5:1])
Sign S = -1
01x00
VINP
AC1(VSS)
VINN
AC0(VREF)
Revision 1.01
© Semtech
January 2011
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