LC78681E Datasheet, PDF (8/23 Pages) Sanyo Semicon Device – Digital Signal Processor for Compact Disc Players

LC78681E
PLL Clock Regeneration Circuit (pin 4: PDO, pin 3: AI, and pin 2: AO)
A PLL comprising a VCO can be made with an LA9210. Output from the PDO pin goes positive when the VCO phase is
lagging.
VCO Half-Frequency Clock (pin 18: PCK)
This pin monitors a signal generated by dividing the VCO frequency by two. This signal has an average frequency of
4.3218 MHz.
Frame Synchronization Detector Monitor (pin 19: FSEQ)
FSEQ is latched high for one frame when the frame sync (true synchronization signal) recovered from the EFM signal
matches the sync timing generated by an internal counter.
Servo Command Function (pin 51: RWC, pin 53: COIN, pin 54: CQCK and pin 62: CS)
Commands can be input by setting RWC high and issuing the command synchronized to the CQCK clock from COIN.
Focus start
Track jump
Mute control
Disc motor control
Other control commands
1-byte commands
Track count
2-byte command
1. 1-byte Commands
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