LC78681E Datasheet, PDF (6/23 Pages) Sanyo Semicon Device – Digital Signal Processor for Compact Disc Players

LC78681E
Pin Description
Figure 3 Subcode Output
No.
Name
1
TEST1
2
AO
3
AI
4
PDO
5
V_SS
6
EFMO
7
EFMO
8
EFMIN
9
TEST2
10
CLV⁺
11
CLV^–
12
V/P
13
FOCS
14
FST
15
FZD
16
HFL
17
TES
18
PCK
19
FSEQ
20
TOFF
21
TGL
22
THLD
23
TEST3
24
V_DD
25
JP⁺
26
JP^–
27
DEMO
28
TEST4
29
EMPH
30
NC
31
WCLK
32
TEST7
33
LRCLK
34
NC
35
DFOUT
36
DACLK
37
TEST6
I/O
Description
I
LSI test input. Normally unconnected.
O
I
LPin for input of the on-chip VCO output from the LA9210 (8.6436 MHz). Phase detector output (PDO) is phased
output with the EFM signal, set so that frequency is raised by positive voltage.
O
— GND
O
O
Inputs 1 to 2 V_PP HF signal to EFMIN. Complementary EFM signal output is made from EFMO and EFMO via the
amplitude limiter. These are used for slice level control.
I
I
LSI test input. Normally unconnected.
O
Disc motor control outputs.
O
O Output is high with constant linear velocity rough servo, and low during phase control
O
O
Focus servo is switched off when FOCS is high. Lens is lowered by FST and raised gradually when FOCS is high.
Generation of FZD resets FOCS. Used for focus servo control.
I
I
Generates kick pulse, JP⁺, or JP^– according to track jump command. Jumps the specified number of tracks (1, 2, 4,
I
16, 32, 64, or 128).
O 4.3218 MHz PCK monitor output.
High when SYNC (true frame sync) detected from the EFM signal matches SYNC from counter (interleaving frame
O
sync). (Single-frame latch output.)
O
O
Generates kick pulse, JP⁺, or JP^– according to track jump command. Jumps the specified number of tracks (1, 2, 4,
16, 32, 64, or 128).
O
I
LSI test input. Normally unconnected.
— +5 V
O
Generates kick pulse, JP⁺, or JP^– according to track jump command. Jumps the specified number of tracks (1, 2, 4,
O ^{16, 32, 64, or 128).}
I
Sound generation function for set adjustment.
I
LSI test input. Normally unconnected.
O Deemphasis required when high.
Not connected.
O Signal output to D/A converter. Outputs latch signal and signals for left-right switching and sample holding.
O LSI test input. Normally unconnected.
O Signal output to D/A converter. Outputs latch signal and signals for left-right switching and sample holding.
Not connected.
O
Signal output to D/A converter. Outputs latch signal and signals for left-right switching and sample holding.
O
O LSI test input. Normally unconnected.
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