LC78681E Datasheet, PDF (22/23 Pages) Sanyo Semicon Device – Digital Signal Processor for Compact Disc Players

LC78681E
Description of Block Operation
1. RAM Address Control
The LC78681E incorporates an 8-bit × 2-kbyte RAM buffer, allowing address control to be used to remove from the
EFM demodulation data such timing variations, or jitter, that are caused by variations in disc motor speed. The buffer
can absorb up to ±4 frames of jitter. The buffer controller constantly monitors buffer free space and adjusts the CLV
servocontroller divider ratio to keep the data write address in the middle of the buffer (i.e., at zero). If the ±4-frame
limit is exceeded, the write address is forced to ±0, and the output is muted for 128 frames because the resulting error
cannot be handled by normal error processing algorithms.
Position
–4 or less
–3
–2
–1
±0
+1
+2
+3
+4 or more
Force to ±0
589
589
589
588
587
587
587
Force to ±0
Division ratio or processing
Increase ratio
Standard ratio
Decrease ratio
C1 and C2 Error Correction
After EFM demodulation, data is written to the internal RAM, jitter is absorbed, and the processing described below is
carried out under uniform timing according to the crystal clock. First, the C1 stage involves error detection and
correction, determination of the C1 flags, and writing to the C1 flag register. Next, the C2 stage involves error detection
and correction, determination of the C2 flags, and writing to the internal RAM.
C1 flag
No errors
1 error
2 errors
3 errors or more
Error correction and flag processing
No correction required
Flag reset
Correction
Flag reset
Correction
Flag set
Correction not possible
Flag set
C2 flag
Error correction and flag processing
No errors
No correction required
Flag reset
1 error
Correction
Flag reset
2 errors
Depends on C1 flags^*1
3 errors or more
Depends on C1 flags^*2
Notes: 1. If the error positions determined in the C2 stage match the C1 flags, correction is carried out and the flags are reset. However, if there are seven
or more C1 flags, no correction is made (because of the danger of erroneous correction), and the C1 flags are taken as the C2 flags without
change. If one error position matches but another does not, correction cannot be performed. Moreover, if there are five or fewer C1 flags, the
results of the C1 stage may be incorrect, and the flag is set. If there are six or more, the situation is handled as uncorrectable, and the C1 flags
are taken as the C2 flags without change. Correction is not possible if even only one error position is different, and the flags are set even if there
are two or fewer C1 flags, because such data may be erroneous even if it passes the C1 stage.
2. If there are three or more errors and correction is determined to be impossible, no correction is made; if there are two or fewer C1 flags, data
which passes the C1 stage may still be corrupt, and so the flags are set. Otherwise the C1 flags are taken as the C2 flags without change.
No. 4521-22/23