LV24010LP Datasheet, PDF (7/18 Pages) Sanyo Semicon Device – Bi-CMOS LSI Compact Portable Equipment 1-Chip FM+RDS Tuner IC

LV24010LP
Digital interface specification (Interface specification: reference)
(1) 3-wire bus (For communication line)
Access to the LV24010 is done through the 3-wire bus:
CLOCK Data strobe, input to the LV24010
NR_W
Command (Write or read data), input to the LV24010
DATA
Bi-directional pin: input to the LV24010 when NR_W is high, output from the LV24010 when NR_W is low.
The LV24010 can be configured to generate interrupt through the DATA-line. When interrupt mode is selected, care
should be taken that the DATA-line connection to the application micro-controller also supports interrupt.
When the required timing window for frequency measurements is not generated by the application micro-controller, an
external clock must be connected to CLK_IN pin of the LV24010
(2) Register map (For register map)
The LV24020 registers are divided in 2 blocks:
Block 01h
Status and measurement
Block 02h
Radio Control
Block 04h
RDS control
To access a register in a block, the block must be first selected by writing the block number to the BLK_SEL register.
Block selection can be skipped for subsequent accesses to other registers in the same block.
The mapping is as follows:
Block
Address
Register name
Access
Operation
01h
00h
CHIP_ID
R
Chip identification
01h
BLK_SEL
W
Block Select
02h
MSRC_SEL
W
Measure source select
03h
FM_OSC
W
DAC control for FM-RF oscillator
04h
SD_OSC
W
DAC control for stereo decoder oscillator
05h
IF_OSC
W
DAC control for IF oscillator
06h
CNT_CTRL
W
Counter control
07h
NA
-
08h
IRQ_MSK
W
Interrupt mask
09h
FM_CAP
W
CAP bank control for RF-frequency
0Ah
CNT_L
R
Counter value low byte
0Bh
CNT_H
R
Counter value high byte
0Ch
CTRL_STAT
R
Control status
0Dh
RADIO_STAT
R
Radio station status
0Eh
IRQ_ID
R
Interrupt identify
0Fh
IRQ_OUT
W
Set Interrupt on DATA-line
02h
01h
BLK_SEL
W
Access register 01h of block 1
02h
RADIO_CTRL1
W
Radio control 1
03h
IF_CENTER
W
IF Center Frequency
04h
NA
W
05h
IF_BW
W
IF Bandwidth
06h
RADIO_CTRL2
W
Radio Control 2
07h
RADIO_CTRL3
W
Radio control 3
08h
STEREO_CTRL
W
Stereo Control
09h
AUDIO_CTRL1
W
Audio Control 1
0Ah
AUDIO_CTRL2
W
Audio Control 1
0Bh
PW_SCTRL
W
Power and soft control
04h
01h
BLK_SEL
W
Access register 01h of block 1
03h
RDS_FLTDAC
W
DAC control for RDS filter
04h
RDAT_L
R
Demodulated RDS data - low byte
05h
RDAT_H
R
Demodulated RDS data – high byte
06h
RDS_CTRL
W
RDS control
07h
RDS_OSC
W
DAC control for RDS PLL oscillator
08h
NA
-
09h
RDS_INPS
W
RDS input setting
Registers with blank colum are not defined and should not be accessed.
No.A0466-7/18