LV24010LP Datasheet, PDF (15/18 Pages) Sanyo Semicon Device – Bi-CMOS LSI Compact Portable Equipment 1-Chip FM+RDS Tuner IC

LV24010LP
Block 4, Register 06h - RDS_CTRL - RDS Control Register (Write-only)
7
6
5
4
3
2
RDS_EN_L
RDS_PM
RDSLRG
RDSITG_L
RDSBW1
RDSBW0
bit 7:
RDS_EN_L: Enable RDS (active low).
0 = RDS is switched ON.
1 = RDS is switched OFF.
1
RDCNT_EN
bit 6:
RDS_PM: RDS PLL mute bit.
0 = RDS PLL is un-muted (normal operation mode).
1 = RDS PLL is muted (calibration mode).
bit 5:
RDSLRG: RDS lock range.
0 = Normal lock range.
1 = Lock range × 2.
bit 4:
RDSITG_L: RDS integrator.
0 = Enable RDS integrator.
1 = Disable RDS integrator.
bit 3-2:
RDSBW[1:0]: RDS Band Width Bits.
00 = RDS Bandwidth is 2.5 kHz.
01 = RDS Bandwidth is 3.5 kHz.
10 = RDS Bandwidth is 4.5 kHz.
11 = RDS Bandwidth is 5.5 kHz.
bit 1:
RDCNT_EN: Enable RDS received bit counter.
0 = Disable RDS counter.
1 = Enable RDS counter (normal mode).
Note: The RDS received bit counter should be enabled when RDS is enabled.
bit 0:
RDCNT_RS: Reset RDS received bit counter.
0 = Reset is switched OFF (normal mode).
1 = Reset is switched ON.
Note: Generate RDS counter reset by making this bit high then low. This will flush the received RDS data FIFO.
0
RDCNT_RS
Block 4, Register 07h - RDS_OSC - RDS PLL Oscillator Register (Write-only)
7
6
5
4
3
2
1
0
RDOSC[7:0]
bit 7-0:
RDOSC[7:0]: DAC value for RDS PLL oscillator.
Note: Positive DAC control (i.e. the frequency increases with the register’s value).
Block 4, Register 09h - RDS_INPS - RDS Input Setting Register (Write-only)
7
6
5
4
3
2
Reserved
Reserved
Reserved
Reserved
RGAIN
RVREF
bit 7-4:
Reserved: Must be programmed with 0000b.
bit 3:
RDS_PM: RDS PLL mute bit.
0 = RDS PLL is un-muted (normal operation mode).
1 = RDS PLL is muted (calibration mode).
bit 5:
RGAIN: Gain control.
0 = 11 ×.
1 = 8 ×.
bit 2:
RVREF: Measure RDS Vref.
0 = Disable.
1 = Enable (test purpose only).
bit 1:
MPXDIV: MPX input divider.
0 =1:3.
1 =1:1.
bit 0:
EN_RNH: RDS notch.
0 = Disable.
1 = Enable.
1
MPXDIV
0
EN_RNH
No.A0466-15/18