LV24010LP Datasheet, PDF (14/18 Pages) Sanyo Semicon Device – Bi-CMOS LSI Compact Portable Equipment 1-Chip FM+RDS Tuner IC

LV24010LP
Block 2, Register 0Ah - AUDIO_CTRL2 - Audio Control 2 Register (Write-only)
7
6
5
4
3
2
Reserved
Reserved
DEEMP
Reserved
Reserved
Reserved
bit 7-6:
bit 5:
bit 4-0:
Reserved: should be written with 11b.
DEEMP: De-emphasis bit.
0 = De-emphasis 50µs.
1 = De-emphasis 75µs.
Reserved: should be written with 00000b.
1
Reserved
Block 2, Register 0Bh - PW_SCTRL - Power and Soft Control Register (Write-only)
7
6
5
4
3
2
1
SS_CTRL
SM_CTRL
Reserved
bit 7-5:
SS_CTRL: Soft stereo control bits (8 levels).
000b = Minimal soft stereo (off).
111b = Maximal soft stereo level.
bit 4-2:
SM_CTRL: Soft audio mute bits (8 levels).
000b = Minimal audio mute (off).
111b = Maximal soft audio mute level.
bit 1:
Reserved: should be written with 0.
bit 0:
PW_RAD: Radio circuitry power bit.
0 = Radio circuitry is switched OFF.
1 = Switch radio circuitry ON.
Note: PW_RAD is 0 at power up.
Block 4, Register 03h - RDS_FLTDAC - RDS Filter DAC Register (Write-only)
7
6
5
4
3
2
1
RFLTDAC[7:0]
bit 7-0:
RFLTDAC[7:0]: DAC value for RDS filter.
Note: This register should be programmed with 95% of the value of RDS_OSC register.
Block 4, Register 04h - RDAT_L - RDS Data Low Register (Read-only)
7
6
5
4
3
2
1
RD_L[7:0]
bit 7-0:
RD_L[7:0]: Low byte of the RDS data.
Note: bit 0 contains the first received bit.
Block 4, Register 05h - RDAT_H - RDS Data High Register (Read-only)
7
6
5
4
3
2
1
RD_L[7:0]
bit 7-0:
RD_H[7:0]: High byte of the RDS data.
Note: bit 0 contains the first received bit.
0
Reserved
0
PW_RAD
0
0
0
No.A0466-14/18