LC87FBL08A Datasheet, PDF (27/28 Pages) Sanyo Semicon Device – 8K-byte FROM and 256-byte RAM integrated 8-bit 1-chip Microcontroller

VDD
Unknown-state
(POUKS)
RES
LC87FBL08A
(a)
(b)
POR release voltage
(PORRL)
Reset period
100μs or longer
Reset period
Figure 7 Waveform observed when only POR is used (LVD not used)
(RESET pin: Pull-up resistor RRES only)
• The POR function generates a reset only when power is turned on starting at the VSS level.
• No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level
as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an
external reset circuit.
• A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on
again after this condition continues for 100μs or longer.
LVD hysteresis width
(LVHYS)
LVD release voltage
(LVDET+LVHYS)
VDD
Unknown-state
(LVUKS)
RES
Reset period
Reset period
Reset period
LVD reset voltage
(LVDET)
Figure 8 Waveform observed when both POR and LVD functions are used
(RESET pin: Pull-up resistor RRES only)
• Resets are generated both when power is turned on and when the power level lowers.
• A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection
level.
No.A1955-27/28